src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "program/prog_parameter.h"
  26
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_batchbuffer.h"
  29 #include "intel_tex.h"
  30 #include "intel_fbo.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35 #include "brw_wm.h"
  36
  37 static void
  38 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
  39 {
  40    switch (tiling) {
  41    case I915_TILING_NONE:
  42       surf->ss0.tiled_surface = 0;
  43       surf->ss0.tile_walk = 0;
  44       break;
  45    case I915_TILING_X:
  46       surf->ss0.tiled_surface = 1;
  47       surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
  48       break;
  49    case I915_TILING_Y:
  50       surf->ss0.tiled_surface = 1;
  51       surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
  52       break;
  53    }
  54 }
  55
  56 static void
  57 gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
  58 {
  59    struct brw_context *brw = brw_context(ctx);
  60    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
  61    struct intel_texture_object *intelObj = intel_texture_object(tObj);
  62    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
  63    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
  64    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
  65    struct gen7_surface_state *surf;
  66    int width, height, depth;
  67
  68    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
  69
  70    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  71                           sizeof(*surf), 32, &brw->bind.surf_offset[surf_index]);
  72    memset(surf, 0, sizeof(*surf));
  73
  74    surf->ss0.surface_type = translate_tex_target(tObj->Target);
  75    surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
  76                                                    firstImage->InternalFormat,
  77                                                    sampler->DepthMode,
  78                                                    sampler->sRGBDecode);
  79    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
  80       surf->ss0.cube_pos_x = 1;
  81       surf->ss0.cube_pos_y = 1;
  82       surf->ss0.cube_pos_z = 1;
  83       surf->ss0.cube_neg_x = 1;
  84       surf->ss0.cube_neg_y = 1;
  85       surf->ss0.cube_neg_z = 1;
  86    }
  87
  88    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
  89
  90    /* ss0 remaining fields:
  91     * - is_array
  92     * - vertical_alignment
  93     * - horizontal_alignment
  94     * - vert_line_stride (exists on gen6 but we ignore it)
  95     * - vert_line_stride_ofs (exists on gen6 but we ignore it)
  96     * - surface_array_spacing
  97     * - render_cache_read_write (exists on gen6 but ignored here)
  98     */
  99
 100    surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */
 101
 102    surf->ss2.width = width - 1;
 103    surf->ss2.height = height - 1;
 104
 105    surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 106    surf->ss3.depth = depth - 1;
 107
 108    /* ss4: ignored? */
 109
 110    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 111    surf->ss5.min_lod = 0;
 112
 113    /* ss5 remaining fields:
 114     * - x_offset (N/A for textures?)
 115     * - y_offset (ditto)
 116     * - cache_control
 117     */
 118
 119    /* Emit relocation to surface contents */
 120    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 121                            brw->bind.surf_offset[surf_index] +
 122                            offsetof(struct gen7_surface_state, ss1),
 123                            intelObj->mt->region->bo, 0,
 124                            I915_GEM_DOMAIN_SAMPLER, 0);
 125 }
 126
 127 /**
 128  * Create the constant buffer surface.  Vertex/fragment shader constants will
 129  * be read from this buffer with Data Port Read instructions/messages.
 130  */
 131 void
 132 gen7_create_constant_surface(struct brw_context *brw,
 133                              drm_intel_bo *bo,
 134                              int width,
 135                              uint32_t *out_offset)
 136 {
 137    const GLint w = width - 1;
 138    struct gen7_surface_state *surf;
 139
 140    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 141                           sizeof(*surf), 32, out_offset);
 142    memset(surf, 0, sizeof(*surf));
 143
 144    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
 145    surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 146
 147    surf->ss0.render_cache_read_write = 1;
 148
 149    assert(bo);
 150    surf->ss1.base_addr = bo->offset; /* reloc */
 151
 152    surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 153    surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 154    surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 155    surf->ss3.pitch = (width * 16) - 1; /* ignored?? */
 156    gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
 157
 158    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 159     * bspec ("Data Cache") says that the data cache does not exist as
 160     * a separate cache and is just the sampler cache.
 161     */
 162    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 163                            (*out_offset +
 164                             offsetof(struct gen7_surface_state, ss1)),
 165                            bo, 0,
 166                            I915_GEM_DOMAIN_SAMPLER, 0);
 167 }
 168
 169 static void
 170 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 171 {
 172    struct gen7_surface_state *surf;
 173
 174    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 175                           sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
 176    memset(surf, 0, sizeof(*surf));
 177
 178    surf->ss0.surface_type = BRW_SURFACE_NULL;
 179    surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 180 }
 181
 182 /**
 183  * Sets up a surface state structure to point at the given region.
 184  * While it is only used for the front/back buffer currently, it should be
 185  * usable for further buffers when doing ARB_draw_buffer support.
 186  */
 187 static void
 188 gen7_update_renderbuffer_surface(struct brw_context *brw,
 189                                  struct gl_renderbuffer *rb,
 190                                  unsigned int unit)
 191 {
 192    struct intel_context *intel = &brw->intel;
 193    struct gl_context *ctx = &intel->ctx;
 194    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 195    struct intel_region *region = irb->mt->region;
 196    struct gen7_surface_state *surf;
 197    uint32_t tile_x, tile_y;
 198
 199    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 200                           sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
 201    memset(surf, 0, sizeof(*surf));
 202
 203    switch (irb->Base.Format) {
 204    case MESA_FORMAT_SARGB8:
 205       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 206          surfaces to the blend/update as sRGB */
 207       if (ctx->Color.sRGBEnabled)
 208          surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
 209       else
 210          surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 211       break;
 212    default:
 213       assert(brw_render_target_supported(intel, irb->Base.Format));
 214       surf->ss0.surface_format = brw->render_target_format[irb->Base.Format];
 215       if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
 216          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 217                        __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
 218       }
 219        break;
 220    }
 221
 222    surf->ss0.surface_type = BRW_SURFACE_2D;
 223    /* reloc */
 224    surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 225    surf->ss1.base_addr += region->bo->offset; /* reloc */
 226
 227    assert(brw->has_surface_tile_offset);
 228    /* Note that the low bits of these fields are missing, so
 229     * there's the possibility of getting in trouble.
 230     */
 231    assert(tile_x % 4 == 0);
 232    assert(tile_y % 2 == 0);
 233    surf->ss5.x_offset = tile_x / 4;
 234    surf->ss5.y_offset = tile_y / 2;
 235
 236    surf->ss2.width = rb->Width - 1;
 237    surf->ss2.height = rb->Height - 1;
 238    gen7_set_surface_tiling(surf, region->tiling);
 239    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 240
 241    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 242                            brw->bind.surf_offset[unit] +
 243                            offsetof(struct gen7_surface_state, ss1),
 244                            region->bo,
 245                            surf->ss1.base_addr - region->bo->offset,
 246                            I915_GEM_DOMAIN_RENDER,
 247                            I915_GEM_DOMAIN_RENDER);
 248 }
 249
 250 void
 251 gen7_init_vtable_surface_functions(struct brw_context *brw)
 252 {
 253    struct intel_context *intel = &brw->intel;
 254
 255    intel->vtbl.update_texture_surface = gen7_update_texture_surface;
 256    intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 257    intel->vtbl.update_null_renderbuffer_surface =
 258       gen7_update_null_renderbuffer_surface;
 259    intel->vtbl.create_constant_surface = gen7_create_constant_surface;
 260 }