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i965/gen9: Prepare surface state setup for lossless compression
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
29
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
33
34 #include "brw_blorp.h"
35
36
37 /* SURFACE_STATE for renderbuffer or texture surface (see
38 * brw_update_renderbuffer_surface and brw_update_texture_surface)
39 */
40 static uint32_t
41 gen8_blorp_emit_surface_state(struct brw_context *brw,
42 const struct brw_blorp_surface_info *surface,
43 uint32_t read_domains, uint32_t write_domain,
44 bool is_render_target)
45 {
46 uint32_t wm_surf_offset;
47 const struct intel_mipmap_tree *mt = surface->mt;
48 const uint32_t mocs_wb = is_render_target ?
49 (brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE) :
50 (brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB);
51 const uint32_t tiling = surface->map_stencil_as_y_tiled
52 ? I915_TILING_Y : mt->tiling;
53 uint32_t tile_x, tile_y;
54
55 uint32_t *surf = gen8_allocate_surface_state(brw, &wm_surf_offset, -1);
56
57 surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
58 surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
59 gen8_vertical_alignment(brw, mt, BRW_SURFACE_2D) |
60 gen8_horizontal_alignment(brw, mt, BRW_SURFACE_2D) |
61 gen8_surface_tiling_mode(tiling);
62
63 surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
64
65 surf[2] = SET_FIELD(surface->width - 1, GEN7_SURFACE_WIDTH) |
66 SET_FIELD(surface->height - 1, GEN7_SURFACE_HEIGHT);
67
68 uint32_t pitch_bytes = mt->pitch;
69 if (surface->map_stencil_as_y_tiled)
70 pitch_bytes *= 2;
71 surf[3] = pitch_bytes - 1;
72
73 surf[4] = gen7_surface_msaa_bits(surface->num_samples,
74 surface->msaa_layout);
75
76 if (surface->mt->mcs_mt) {
77 surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
78 SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1,
79 GEN8_SURFACE_AUX_PITCH) |
80 gen8_get_aux_mode(brw, mt);
81 } else {
82 surf[6] = 0;
83 }
84
85 gen8_emit_fast_clear_color(brw, mt, surf);
86 surf[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
87 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
88 SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
89 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
90
91 /* reloc */
92 *((uint64_t *)&surf[8]) =
93 brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y) +
94 mt->bo->offset64;
95
96 /* Note that the low bits of these fields are missing, so there's the
97 * possibility of getting in trouble.
98 */
99 assert(tile_x % 4 == 0);
100 assert(tile_y % 4 == 0);
101 surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
102 SET_FIELD(tile_y / 4, GEN8_SURFACE_Y_OFFSET);
103
104 if (brw->gen >= 9) {
105 /* Disable Mip Tail by setting a large value. */
106 surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
107 }
108
109 if (surface->mt->mcs_mt) {
110 *((uint64_t *) &surf[10]) = surface->mt->mcs_mt->bo->offset64;
111 drm_intel_bo_emit_reloc(brw->batch.bo,
112 wm_surf_offset + 10 * 4,
113 surface->mt->mcs_mt->bo, 0,
114 read_domains, write_domain);
115 }
116
117 /* Emit relocation to surface contents */
118 drm_intel_bo_emit_reloc(brw->batch.bo,
119 wm_surf_offset + 8 * 4,
120 mt->bo,
121 surf[8] - mt->bo->offset64,
122 read_domains, write_domain);
123
124 return wm_surf_offset;
125 }
126
127 static uint32_t
128 gen8_blorp_emit_blend_state(struct brw_context *brw,
129 const struct brw_blorp_params *params)
130 {
131 uint32_t blend_state_offset;
132
133 assume(params->num_draw_buffers);
134
135 const unsigned size = 4 + 8 * params->num_draw_buffers;
136 uint32_t *blend = (uint32_t *)brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
137 size, 64,
138 &blend_state_offset);
139 memset(blend, 0, size);
140
141 for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
142 if (params->color_write_disable[0])
143 blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_RED;
144 if (params->color_write_disable[1])
145 blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_GREEN;
146 if (params->color_write_disable[2])
147 blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_BLUE;
148 if (params->color_write_disable[3])
149 blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_ALPHA;
150
151 blend[1 + 2 * i + 1] = GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE |
152 GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE |
153 GEN8_BLEND_COLOR_CLAMP_RANGE_RTFORMAT;
154 }
155
156 return blend_state_offset;
157 }
158
159 static void
160 gen8_blorp_emit_disable_constant_state(struct brw_context *brw,
161 unsigned opcode)
162 {
163 BEGIN_BATCH(11);
164 OUT_BATCH(opcode << 16 | (11 - 2));
165 OUT_BATCH(0);
166 OUT_BATCH(0);
167 OUT_BATCH(0);
168 OUT_BATCH(0);
169 OUT_BATCH(0);
170 OUT_BATCH(0);
171 OUT_BATCH(0);
172 OUT_BATCH(0);
173 OUT_BATCH(0);
174 OUT_BATCH(0);
175 ADVANCE_BATCH();
176 }
177
178 static void
179 gen8_blorp_emit_disable_binding_table(struct brw_context *brw,
180 unsigned opcode)
181 {
182
183 BEGIN_BATCH(2);
184 OUT_BATCH(opcode << 16 | (2 - 2));
185 OUT_BATCH(0);
186 ADVANCE_BATCH();
187 }
188
189 /* 3DSTATE_VS
190 *
191 * Disable vertex shader.
192 */
193 static void
194 gen8_blorp_emit_vs_disable(struct brw_context *brw)
195 {
196 BEGIN_BATCH(9);
197 OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
198 OUT_BATCH(0);
199 OUT_BATCH(0);
200 OUT_BATCH(0);
201 OUT_BATCH(0);
202 OUT_BATCH(0);
203 OUT_BATCH(0);
204 OUT_BATCH(0);
205 OUT_BATCH(0);
206 ADVANCE_BATCH();
207 }
208
209 /* 3DSTATE_HS
210 *
211 * Disable the hull shader.
212 */
213 static void
214 gen8_blorp_emit_hs_disable(struct brw_context *brw)
215 {
216 BEGIN_BATCH(9);
217 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
218 OUT_BATCH(0);
219 OUT_BATCH(0);
220 OUT_BATCH(0);
221 OUT_BATCH(0);
222 OUT_BATCH(0);
223 OUT_BATCH(0);
224 OUT_BATCH(0);
225 OUT_BATCH(0);
226 ADVANCE_BATCH();
227 }
228
229 /* 3DSTATE_DS
230 *
231 * Disable the domain shader.
232 */
233 static void
234 gen8_blorp_emit_ds_disable(struct brw_context *brw)
235 {
236 const int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
237 BEGIN_BATCH(ds_pkt_len);
238 OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
239 for (int i = 0; i < ds_pkt_len - 1; i++)
240 OUT_BATCH(0);
241 ADVANCE_BATCH();
242 }
243
244 /* 3DSTATE_GS
245 *
246 * Disable the geometry shader.
247 */
248 static void
249 gen8_blorp_emit_gs_disable(struct brw_context *brw)
250 {
251 BEGIN_BATCH(10);
252 OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
253 OUT_BATCH(0);
254 OUT_BATCH(0);
255 OUT_BATCH(0);
256 OUT_BATCH(0);
257 OUT_BATCH(0);
258 OUT_BATCH(0);
259 OUT_BATCH(0);
260 OUT_BATCH(0);
261 OUT_BATCH(0);
262 ADVANCE_BATCH();
263 }
264
265 /* 3DSTATE_STREAMOUT
266 *
267 * Disable streamout.
268 */
269 static void
270 gen8_blorp_emit_streamout_disable(struct brw_context *brw)
271 {
272 BEGIN_BATCH(5);
273 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (5 - 2));
274 OUT_BATCH(0);
275 OUT_BATCH(0);
276 OUT_BATCH(0);
277 OUT_BATCH(0);
278 ADVANCE_BATCH();
279 }
280
281 static void
282 gen8_blorp_emit_raster_state(struct brw_context *brw)
283 {
284 BEGIN_BATCH(5);
285 OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
286 OUT_BATCH(GEN8_RASTER_CULL_NONE);
287 OUT_BATCH_F(0);
288 OUT_BATCH_F(0);
289 OUT_BATCH_F(0);
290 ADVANCE_BATCH();
291 }
292
293 static void
294 gen8_blorp_emit_sbe_state(struct brw_context *brw,
295 const struct brw_blorp_params *params)
296 {
297 /* 3DSTATE_SBE */
298 {
299 const unsigned sbe_cmd_length = brw->gen == 8 ? 4 : 6;
300 BEGIN_BATCH(sbe_cmd_length);
301 OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
302 OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
303 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
304 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
305 BRW_SF_URB_ENTRY_READ_OFFSET <<
306 GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT |
307 GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
308 GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET);
309 OUT_BATCH(0);
310 OUT_BATCH(0);
311 if (sbe_cmd_length >= 6) {
312 OUT_BATCH(GEN9_SBE_ACTIVE_COMPONENT_XYZW << (0 << 1));
313 OUT_BATCH(0);
314 }
315 ADVANCE_BATCH();
316 }
317
318 {
319 BEGIN_BATCH(11);
320 OUT_BATCH(_3DSTATE_SBE_SWIZ << 16 | (11 - 2));
321
322 /* Output DWords 1 through 8: */
323 for (int i = 0; i < 8; i++) {
324 OUT_BATCH(0);
325 }
326
327 OUT_BATCH(0); /* wrapshortest enables 0-7 */
328 OUT_BATCH(0); /* wrapshortest enables 8-15 */
329 ADVANCE_BATCH();
330 }
331 }
332
333 static void
334 gen8_blorp_emit_sf_config(struct brw_context *brw)
335 {
336 /* See gen6_blorp_emit_sf_config() */
337 BEGIN_BATCH(4);
338 OUT_BATCH(_3DSTATE_SF << 16 | (4 - 2));
339 OUT_BATCH(0);
340 OUT_BATCH(0);
341 OUT_BATCH(GEN6_SF_LINE_AA_MODE_TRUE);
342 ADVANCE_BATCH();
343 }
344
345 /**
346 * Disable thread dispatch (dw5.19) and enable the HiZ op.
347 */
348 static void
349 gen8_blorp_emit_wm_state(struct brw_context *brw)
350 {
351 BEGIN_BATCH(2);
352 OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
353 OUT_BATCH(GEN7_WM_LINE_AA_WIDTH_1_0 |
354 GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 |
355 GEN7_WM_POINT_RASTRULE_UPPER_RIGHT);
356 ADVANCE_BATCH();
357 }
358
359 /**
360 * 3DSTATE_PS
361 *
362 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
363 * that, thread dispatch info must still be specified.
364 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
365 * valid range for this field is [0x3, 0x2f].
366 * - A dispatch mode must be given; that is, at least one of the
367 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
368 * discovered through simulator error messages.
369 */
370 static void
371 gen8_blorp_emit_ps_config(struct brw_context *brw,
372 const struct brw_blorp_params *params)
373 {
374 const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
375 uint32_t dw3, dw5, dw6, dw7;
376
377 dw3 = dw5 = dw6 = dw7 = 0;
378 dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
379
380 dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
381
382 if (params->src.mt) {
383 dw3 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
384 dw3 |= 2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* Two surfaces */
385 } else {
386 dw3 |= 1 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* One surface */
387 }
388
389 dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
390 dw7 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
391
392 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
393 * it implicitly scales for different GT levels (which have some # of PSDs).
394 *
395 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
396 */
397 if (brw->gen >= 9)
398 dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
399 else
400 dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
401
402 dw6 |= GEN7_PS_POSOFFSET_NONE;
403 dw6 |= params->fast_clear_op;
404
405 BEGIN_BATCH(12);
406 OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
407 OUT_BATCH(params->wm_prog_kernel);
408 OUT_BATCH(0);
409 OUT_BATCH(dw3);
410 OUT_BATCH(0);
411 OUT_BATCH(0);
412 OUT_BATCH(dw6);
413 OUT_BATCH(dw7);
414 OUT_BATCH(0);
415 OUT_BATCH(0);
416 OUT_BATCH(0);
417 OUT_BATCH(0);
418 ADVANCE_BATCH();
419 }
420
421 static void
422 gen8_blorp_emit_ps_blend(struct brw_context *brw)
423 {
424 BEGIN_BATCH(2);
425 OUT_BATCH(_3DSTATE_PS_BLEND << 16 | (2 - 2));
426 OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
427 ADVANCE_BATCH();
428 }
429
430 static void
431 gen8_blorp_emit_ps_extra(struct brw_context *brw,
432 const struct brw_blorp_params *params)
433 {
434 const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
435 uint32_t dw1 = 0;
436
437 dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
438
439 if (params->src.mt) {
440 dw1 |= GEN8_PSX_KILL_ENABLE;
441 dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
442 }
443
444 if (params->dst.num_samples > 1 && prog_data &&
445 prog_data->persample_msaa_dispatch)
446 dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
447
448 BEGIN_BATCH(2);
449 OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
450 OUT_BATCH(dw1);
451 ADVANCE_BATCH();
452 }
453
454 static void
455 gen8_blorp_emit_depth_disable(struct brw_context *brw)
456 {
457 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
458 if (brw->no_depth_or_stencil)
459 return;
460
461 brw_emit_depth_stall_flushes(brw);
462
463 BEGIN_BATCH(8);
464 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
465 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
466 OUT_BATCH(0);
467 OUT_BATCH(0);
468 OUT_BATCH(0);
469 OUT_BATCH(0);
470 OUT_BATCH(0);
471 OUT_BATCH(0);
472 ADVANCE_BATCH();
473
474 BEGIN_BATCH(5);
475 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
476 OUT_BATCH(0);
477 OUT_BATCH(0);
478 OUT_BATCH(0);
479 OUT_BATCH(0);
480 ADVANCE_BATCH();
481
482 BEGIN_BATCH(5);
483 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
484 OUT_BATCH(0);
485 OUT_BATCH(0);
486 OUT_BATCH(0);
487 OUT_BATCH(0);
488 ADVANCE_BATCH();
489 }
490
491 static void
492 gen8_blorp_emit_vf_topology(struct brw_context *brw)
493 {
494 BEGIN_BATCH(2);
495 OUT_BATCH(_3DSTATE_VF_TOPOLOGY << 16 | (2 - 2));
496 OUT_BATCH(_3DPRIM_RECTLIST);
497 ADVANCE_BATCH();
498 }
499
500 static void
501 gen8_blorp_emit_vf_sys_gen_vals_state(struct brw_context *brw)
502 {
503 BEGIN_BATCH(2);
504 OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
505 OUT_BATCH(0);
506 ADVANCE_BATCH();
507 }
508
509 static void
510 gen8_blorp_emit_vf_instancing_state(struct brw_context *brw,
511 unsigned num_elems)
512 {
513 for (unsigned i = 0; i < num_elems; ++i) {
514 BEGIN_BATCH(3);
515 OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
516 OUT_BATCH(i);
517 OUT_BATCH(0);
518 ADVANCE_BATCH();
519 }
520 }
521
522 static void
523 gen8_blorp_emit_vf_state(struct brw_context *brw)
524 {
525 BEGIN_BATCH(2);
526 OUT_BATCH(_3DSTATE_VF << 16 | (2 - 2));
527 OUT_BATCH(0);
528 ADVANCE_BATCH();
529 }
530
531 static void
532 gen8_blorp_emit_depth_stencil_state(struct brw_context *brw,
533 const struct brw_blorp_params *params)
534 {
535 const unsigned pkt_len = brw->gen >= 9 ? 4 : 3;
536
537 BEGIN_BATCH(pkt_len);
538 OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (pkt_len - 2));
539 OUT_BATCH(0);
540 OUT_BATCH(0);
541 if (pkt_len > 3) {
542 OUT_BATCH(0);
543 }
544 ADVANCE_BATCH();
545 }
546
547 static void
548 gen8_blorp_emit_constant_ps(struct brw_context *brw,
549 uint32_t wm_push_const_offset)
550 {
551 const int dwords = brw->gen >= 8 ? 11 : 7;
552 BEGIN_BATCH(dwords);
553 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (dwords - 2));
554
555 if (brw->gen >= 9) {
556 OUT_BATCH(0);
557 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
558 } else {
559 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
560 OUT_BATCH(0);
561 }
562
563 if (brw->gen >= 9) {
564 OUT_BATCH(0);
565 OUT_BATCH(0);
566 OUT_BATCH(0);
567 OUT_BATCH(0);
568 OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
569 wm_push_const_offset);
570 OUT_BATCH(0);
571 OUT_BATCH(0);
572 } else {
573 OUT_BATCH(wm_push_const_offset);
574 OUT_BATCH(0);
575 OUT_BATCH(0);
576 OUT_BATCH(0);
577 OUT_BATCH(0);
578 OUT_BATCH(0);
579 OUT_BATCH(0);
580 OUT_BATCH(0);
581 }
582
583 ADVANCE_BATCH();
584 }
585
586 static uint32_t
587 gen8_blorp_emit_surface_states(struct brw_context *brw,
588 const struct brw_blorp_params *params)
589 {
590 uint32_t wm_surf_offset_renderbuffer;
591 uint32_t wm_surf_offset_texture = 0;
592
593 intel_miptree_used_for_rendering(params->dst.mt);
594
595 wm_surf_offset_renderbuffer =
596 gen8_blorp_emit_surface_state(brw, &params->dst,
597 I915_GEM_DOMAIN_RENDER,
598 I915_GEM_DOMAIN_RENDER,
599 true /* is_render_target */);
600 if (params->src.mt) {
601 const struct brw_blorp_surface_info *surface = &params->src;
602 struct intel_mipmap_tree *mt = surface->mt;
603
604 /* If src is a 2D multisample array texture on Gen7+ using
605 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src layer is the
606 * physical layer holding sample 0. So, for example, if mt->num_samples
607 * == 4, then logical layer n corresponds to layer == 4*n.
608 *
609 * Multisampled depth and stencil surfaces have the samples interleaved
610 * (INTEL_MSAA_LAYOUT_IMS) and therefore the layer doesn't need
611 * adjustment.
612 */
613 const unsigned layer_divider =
614 (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
615 mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
616 MAX2(mt->num_samples, 1) : 1;
617
618 /* Cube textures are sampled as 2D array. */
619 const bool is_cube = mt->target == GL_TEXTURE_CUBE_MAP_ARRAY ||
620 mt->target == GL_TEXTURE_CUBE_MAP;
621 const unsigned depth = (is_cube ? 6 : 1) * mt->logical_depth0;
622 const GLenum target = is_cube ? GL_TEXTURE_2D_ARRAY : mt->target;
623 const unsigned max_level = surface->level + mt->last_level + 1;
624 const unsigned layer = mt->target != GL_TEXTURE_3D ?
625 surface->layer / layer_divider : 0;
626
627 brw->vtbl.emit_texture_surface_state(brw, mt, target,
628 layer, layer + depth,
629 surface->level, max_level,
630 surface->brw_surfaceformat,
631 surface->swizzle,
632 &wm_surf_offset_texture,
633 -1, false, false);
634 }
635
636 return gen6_blorp_emit_binding_table(brw,
637 wm_surf_offset_renderbuffer,
638 wm_surf_offset_texture);
639 }
640
641 /**
642 * \copydoc gen6_blorp_exec()
643 */
644 void
645 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
646 {
647 uint32_t wm_bind_bo_offset = 0;
648
649 if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
650 gen8_upload_state_base_address(brw);
651
652 gen7_blorp_emit_cc_viewport(brw);
653 gen7_l3_state.emit(brw);
654
655 gen7_blorp_emit_urb_config(brw);
656
657 const uint32_t cc_blend_state_offset =
658 gen8_blorp_emit_blend_state(brw, params);
659 gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
660
661 const uint32_t cc_state_offset = gen6_blorp_emit_cc_state(brw);
662 gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
663
664 gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
665 gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
666 gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
667 gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
668
669 const uint32_t wm_push_const_offset =
670 gen6_blorp_emit_wm_constants(brw, params);
671 gen8_blorp_emit_constant_ps(brw, wm_push_const_offset);
672 wm_bind_bo_offset = gen8_blorp_emit_surface_states(brw, params);
673
674 gen8_blorp_emit_disable_binding_table(brw,
675 _3DSTATE_BINDING_TABLE_POINTERS_VS);
676 gen8_blorp_emit_disable_binding_table(brw,
677 _3DSTATE_BINDING_TABLE_POINTERS_HS);
678 gen8_blorp_emit_disable_binding_table(brw,
679 _3DSTATE_BINDING_TABLE_POINTERS_DS);
680 gen8_blorp_emit_disable_binding_table(brw,
681 _3DSTATE_BINDING_TABLE_POINTERS_GS);
682
683 gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
684
685 if (params->src.mt) {
686 const uint32_t sampler_offset =
687 gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
688 gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
689 }
690
691 gen8_emit_3dstate_multisample(brw, params->dst.num_samples);
692 gen6_emit_3dstate_sample_mask(brw,
693 params->dst.num_samples > 1 ?
694 (1 << params->dst.num_samples) - 1 : 1);
695
696 gen8_disable_stages.emit(brw);
697 gen8_blorp_emit_vs_disable(brw);
698 gen8_blorp_emit_hs_disable(brw);
699 gen7_blorp_emit_te_disable(brw);
700 gen8_blorp_emit_ds_disable(brw);
701 gen8_blorp_emit_gs_disable(brw);
702
703 gen8_blorp_emit_streamout_disable(brw);
704 gen6_blorp_emit_clip_disable(brw);
705 gen8_blorp_emit_raster_state(brw);
706 gen8_blorp_emit_sbe_state(brw, params);
707 gen8_blorp_emit_sf_config(brw);
708
709 gen8_blorp_emit_ps_blend(brw);
710 gen8_blorp_emit_ps_extra(brw, params);
711
712 gen8_blorp_emit_ps_config(brw, params);
713
714 gen8_blorp_emit_depth_stencil_state(brw, params);
715 gen8_blorp_emit_wm_state(brw);
716
717 gen8_blorp_emit_depth_disable(brw);
718 gen7_blorp_emit_clear_params(brw, params);
719 gen6_blorp_emit_drawing_rectangle(brw, params);
720 gen8_blorp_emit_vf_topology(brw);
721 gen8_blorp_emit_vf_sys_gen_vals_state(brw);
722 gen6_blorp_emit_vertices(brw, params);
723 gen8_blorp_emit_vf_instancing_state(brw, 2);
724 gen8_blorp_emit_vf_state(brw);
725 gen7_blorp_emit_primitive(brw, params);
726
727 if (brw->gen < 9)
728 gen8_write_pma_stall_bits(brw, 0);
729 }