src/mesa/drivers/dri/i965/gen8_blorp.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35
  36
  37 /* SURFACE_STATE for renderbuffer or texture surface (see
  38  * brw_update_renderbuffer_surface and brw_update_texture_surface)
  39  */
  40 static uint32_t
  41 gen8_blorp_emit_surface_state(struct brw_context *brw,
  42                               const struct brw_blorp_surface_info *surface,
  43                               uint32_t read_domains, uint32_t write_domain,
  44                               bool is_render_target)
  45 {
  46    uint32_t wm_surf_offset;
  47    const struct intel_mipmap_tree *mt = surface->mt;
  48    const uint32_t mocs_wb = is_render_target ?
  49                                (brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE) :
  50                                (brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB);
  51    const uint32_t tiling = surface->map_stencil_as_y_tiled
  52       ? I915_TILING_Y : mt->tiling;
  53    uint32_t tile_x, tile_y;
  54
  55    uint32_t *surf = gen8_allocate_surface_state(brw, &wm_surf_offset, -1);
  56
  57    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
  58              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
  59              gen8_vertical_alignment(brw, mt, BRW_SURFACE_2D) |
  60              gen8_horizontal_alignment(brw, mt, BRW_SURFACE_2D) |
  61              gen8_surface_tiling_mode(tiling);
  62
  63    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
  64
  65    surf[2] = SET_FIELD(surface->width - 1, GEN7_SURFACE_WIDTH) |
  66              SET_FIELD(surface->height - 1, GEN7_SURFACE_HEIGHT);
  67
  68    uint32_t pitch_bytes = mt->pitch;
  69    if (surface->map_stencil_as_y_tiled)
  70       pitch_bytes *= 2;
  71    surf[3] = pitch_bytes - 1;
  72
  73    surf[4] = gen7_surface_msaa_bits(surface->num_samples,
  74                                     surface->msaa_layout);
  75
  76    if (surface->mt->mcs_mt) {
  77       surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
  78                 SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1,
  79                           GEN8_SURFACE_AUX_PITCH) |
  80                 gen8_get_aux_mode(brw, mt);
  81    } else {
  82       surf[6] = 0;
  83    }
  84
  85    gen8_emit_fast_clear_color(brw, mt, surf);
  86    surf[7] |= SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
  87               SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
  88               SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
  89               SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
  90
  91     /* reloc */
  92    *((uint64_t *)&surf[8]) =
  93       brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y) +
  94       mt->bo->offset64;
  95
  96    /* Note that the low bits of these fields are missing, so there's the
  97     * possibility of getting in trouble.
  98     */
  99    assert(tile_x % 4 == 0);
 100    assert(tile_y % 4 == 0);
 101    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 102              SET_FIELD(tile_y / 4, GEN8_SURFACE_Y_OFFSET);
 103
 104    if (brw->gen >= 9) {
 105       /* Disable Mip Tail by setting a large value. */
 106       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 107    }
 108
 109    if (surface->mt->mcs_mt) {
 110       *((uint64_t *) &surf[10]) = surface->mt->mcs_mt->bo->offset64;
 111       drm_intel_bo_emit_reloc(brw->batch.bo,
 112                               wm_surf_offset + 10 * 4,
 113                               surface->mt->mcs_mt->bo, 0,
 114                               read_domains, write_domain);
 115    }
 116
 117    /* Emit relocation to surface contents */
 118    drm_intel_bo_emit_reloc(brw->batch.bo,
 119                            wm_surf_offset + 8 * 4,
 120                            mt->bo,
 121                            surf[8] - mt->bo->offset64,
 122                            read_domains, write_domain);
 123
 124    return wm_surf_offset;
 125 }
 126
 127 static uint32_t
 128 gen8_blorp_emit_blend_state(struct brw_context *brw,
 129                             const struct brw_blorp_params *params)
 130 {
 131    uint32_t blend_state_offset;
 132
 133    assume(params->num_draw_buffers);
 134
 135    const unsigned size = 4 + 8 * params->num_draw_buffers;
 136    uint32_t *blend = (uint32_t *)brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
 137                                                  size, 64,
 138                                                  &blend_state_offset);
 139    memset(blend, 0, size);
 140
 141    for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
 142       if (params->color_write_disable[0])
 143          blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_RED;
 144       if (params->color_write_disable[1])
 145          blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_GREEN;
 146       if (params->color_write_disable[2])
 147          blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_BLUE;
 148       if (params->color_write_disable[3])
 149          blend[1 + 2 * i] |= GEN8_BLEND_WRITE_DISABLE_ALPHA;
 150
 151       blend[1 + 2 * i + 1] = GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE |
 152                              GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE |
 153                              GEN8_BLEND_COLOR_CLAMP_RANGE_RTFORMAT;
 154    }
 155
 156    return blend_state_offset;
 157 }
 158
 159 static void
 160 gen8_blorp_emit_disable_constant_state(struct brw_context *brw,
 161                                        unsigned opcode)
 162 {
 163    BEGIN_BATCH(11);
 164    OUT_BATCH(opcode << 16 | (11 - 2));
 165    OUT_BATCH(0);
 166    OUT_BATCH(0);
 167    OUT_BATCH(0);
 168    OUT_BATCH(0);
 169    OUT_BATCH(0);
 170    OUT_BATCH(0);
 171    OUT_BATCH(0);
 172    OUT_BATCH(0);
 173    OUT_BATCH(0);
 174    OUT_BATCH(0);
 175    ADVANCE_BATCH();
 176 }
 177
 178 static void
 179 gen8_blorp_emit_disable_binding_table(struct brw_context *brw,
 180                                       unsigned opcode)
 181 {
 182
 183    BEGIN_BATCH(2);
 184    OUT_BATCH(opcode << 16 | (2 - 2));
 185    OUT_BATCH(0);
 186    ADVANCE_BATCH();
 187 }
 188
 189 /* 3DSTATE_VS
 190  *
 191  * Disable vertex shader.
 192  */
 193 static void
 194 gen8_blorp_emit_vs_disable(struct brw_context *brw)
 195 {
 196    BEGIN_BATCH(9);
 197    OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
 198    OUT_BATCH(0);
 199    OUT_BATCH(0);
 200    OUT_BATCH(0);
 201    OUT_BATCH(0);
 202    OUT_BATCH(0);
 203    OUT_BATCH(0);
 204    OUT_BATCH(0);
 205    OUT_BATCH(0);
 206    ADVANCE_BATCH();
 207 }
 208
 209 /* 3DSTATE_HS
 210  *
 211  * Disable the hull shader.
 212  */
 213 static void
 214 gen8_blorp_emit_hs_disable(struct brw_context *brw)
 215 {
 216    BEGIN_BATCH(9);
 217    OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
 218    OUT_BATCH(0);
 219    OUT_BATCH(0);
 220    OUT_BATCH(0);
 221    OUT_BATCH(0);
 222    OUT_BATCH(0);
 223    OUT_BATCH(0);
 224    OUT_BATCH(0);
 225    OUT_BATCH(0);
 226    ADVANCE_BATCH();
 227 }
 228
 229 /* 3DSTATE_DS
 230  *
 231  * Disable the domain shader.
 232  */
 233 static void
 234 gen8_blorp_emit_ds_disable(struct brw_context *brw)
 235 {
 236    const int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
 237    BEGIN_BATCH(ds_pkt_len);
 238    OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
 239    for (int i = 0; i < ds_pkt_len - 1; i++)
 240       OUT_BATCH(0);
 241    ADVANCE_BATCH();
 242 }
 243
 244 /* 3DSTATE_GS
 245  *
 246  * Disable the geometry shader.
 247  */
 248 static void
 249 gen8_blorp_emit_gs_disable(struct brw_context *brw)
 250 {
 251    BEGIN_BATCH(10);
 252    OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
 253    OUT_BATCH(0);
 254    OUT_BATCH(0);
 255    OUT_BATCH(0);
 256    OUT_BATCH(0);
 257    OUT_BATCH(0);
 258    OUT_BATCH(0);
 259    OUT_BATCH(0);
 260    OUT_BATCH(0);
 261    OUT_BATCH(0);
 262    ADVANCE_BATCH();
 263 }
 264
 265 /* 3DSTATE_STREAMOUT
 266  *
 267  * Disable streamout.
 268  */
 269 static void
 270 gen8_blorp_emit_streamout_disable(struct brw_context *brw)
 271 {
 272    BEGIN_BATCH(5);
 273    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (5 - 2));
 274    OUT_BATCH(0);
 275    OUT_BATCH(0);
 276    OUT_BATCH(0);
 277    OUT_BATCH(0);
 278    ADVANCE_BATCH();
 279 }
 280
 281 static void
 282 gen8_blorp_emit_raster_state(struct brw_context *brw)
 283 {
 284    BEGIN_BATCH(5);
 285    OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
 286    OUT_BATCH(GEN8_RASTER_CULL_NONE);
 287    OUT_BATCH_F(0);
 288    OUT_BATCH_F(0);
 289    OUT_BATCH_F(0);
 290    ADVANCE_BATCH();
 291 }
 292
 293 static void
 294 gen8_blorp_emit_sbe_state(struct brw_context *brw,
 295                           const struct brw_blorp_params *params)
 296 {
 297    /* 3DSTATE_SBE */
 298    {
 299       const unsigned sbe_cmd_length = brw->gen == 8 ? 4 : 6;
 300       BEGIN_BATCH(sbe_cmd_length);
 301       OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
 302       OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
 303                 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 304                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 305                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 306                    GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT |
 307                 GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
 308                 GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET);
 309       OUT_BATCH(0);
 310       OUT_BATCH(0);
 311       if (sbe_cmd_length >= 6) {
 312          OUT_BATCH(GEN9_SBE_ACTIVE_COMPONENT_XYZW << (0 << 1));
 313          OUT_BATCH(0);
 314       }
 315       ADVANCE_BATCH();
 316    }
 317
 318    {
 319       BEGIN_BATCH(11);
 320       OUT_BATCH(_3DSTATE_SBE_SWIZ << 16 | (11 - 2));
 321
 322       /* Output DWords 1 through 8: */
 323       for (int i = 0; i < 8; i++) {
 324          OUT_BATCH(0);
 325       }
 326
 327       OUT_BATCH(0); /* wrapshortest enables 0-7 */
 328       OUT_BATCH(0); /* wrapshortest enables 8-15 */
 329       ADVANCE_BATCH();
 330    }
 331 }
 332
 333 static void
 334 gen8_blorp_emit_sf_config(struct brw_context *brw)
 335 {
 336    /* See gen6_blorp_emit_sf_config() */
 337    BEGIN_BATCH(4);
 338    OUT_BATCH(_3DSTATE_SF << 16 | (4 - 2));
 339    OUT_BATCH(0);
 340    OUT_BATCH(0);
 341    OUT_BATCH(GEN6_SF_LINE_AA_MODE_TRUE);
 342    ADVANCE_BATCH();
 343 }
 344
 345 /**
 346  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 347  */
 348 static void
 349 gen8_blorp_emit_wm_state(struct brw_context *brw)
 350 {
 351    BEGIN_BATCH(2);
 352    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 353    OUT_BATCH(GEN7_WM_LINE_AA_WIDTH_1_0 |
 354              GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 |
 355              GEN7_WM_POINT_RASTRULE_UPPER_RIGHT);
 356    ADVANCE_BATCH();
 357 }
 358
 359 /**
 360  * 3DSTATE_PS
 361  *
 362  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 363  * that, thread dispatch info must still be specified.
 364  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 365  *       valid range for this field is [0x3, 0x2f].
 366  *     - A dispatch mode must be given; that is, at least one of the
 367  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 368  *       discovered through simulator error messages.
 369  */
 370 static void
 371 gen8_blorp_emit_ps_config(struct brw_context *brw,
 372                           const struct brw_blorp_params *params)
 373 {
 374    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 375    uint32_t dw3, dw5, dw6, dw7, ksp0, ksp2;
 376
 377    dw3 = dw5 = dw6 = dw7 = ksp0 = ksp2 = 0;
 378    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 379
 380    if (params->src.mt) {
 381       dw3 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 382       dw3 |= 2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* Two surfaces */
 383    } else {
 384       dw3 |= 1 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT; /* One surface */
 385    }
 386
 387    dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 388    dw7 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 389    dw7 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 390
 391    if (params->wm_prog_data->dispatch_8)
 392       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 393    if (params->wm_prog_data->dispatch_16)
 394       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 395
 396    ksp0 = params->wm_prog_kernel;
 397    ksp2 = params->wm_prog_kernel + params->wm_prog_data->ksp_offset_2;
 398
 399    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 400     * it implicitly scales for different GT levels (which have some # of PSDs).
 401     *
 402     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 403     */
 404    if (brw->gen >= 9)
 405       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 406    else
 407       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 408
 409    dw6 |= GEN7_PS_POSOFFSET_NONE;
 410    dw6 |= params->fast_clear_op;
 411
 412    BEGIN_BATCH(12);
 413    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 414    OUT_BATCH(ksp0);
 415    OUT_BATCH(0);
 416    OUT_BATCH(dw3);
 417    OUT_BATCH(0);
 418    OUT_BATCH(0);
 419    OUT_BATCH(dw6);
 420    OUT_BATCH(dw7);
 421    OUT_BATCH(0); /* kernel 1 pointer */
 422    OUT_BATCH(0);
 423    OUT_BATCH(ksp2);
 424    OUT_BATCH(0);
 425    ADVANCE_BATCH();
 426 }
 427
 428 static void
 429 gen8_blorp_emit_ps_blend(struct brw_context *brw)
 430 {
 431    BEGIN_BATCH(2);
 432    OUT_BATCH(_3DSTATE_PS_BLEND << 16 | (2 - 2));
 433    OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
 434    ADVANCE_BATCH();
 435 }
 436
 437 static void
 438 gen8_blorp_emit_ps_extra(struct brw_context *brw,
 439                          const struct brw_blorp_params *params)
 440 {
 441    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 442    uint32_t dw1 = 0;
 443
 444    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
 445
 446    if (params->src.mt) {
 447       dw1 |= GEN8_PSX_KILL_ENABLE;
 448       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
 449    }
 450
 451    if (params->dst.num_samples > 1 && prog_data &&
 452        prog_data->persample_msaa_dispatch)
 453       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
 454
 455    BEGIN_BATCH(2);
 456    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
 457    OUT_BATCH(dw1);
 458    ADVANCE_BATCH();
 459 }
 460
 461 static void
 462 gen8_blorp_emit_depth_disable(struct brw_context *brw)
 463 {
 464    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
 465    if (brw->no_depth_or_stencil)
 466       return;
 467
 468    brw_emit_depth_stall_flushes(brw);
 469
 470    BEGIN_BATCH(8);
 471    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
 472    OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
 473    OUT_BATCH(0);
 474    OUT_BATCH(0);
 475    OUT_BATCH(0);
 476    OUT_BATCH(0);
 477    OUT_BATCH(0);
 478    OUT_BATCH(0);
 479    ADVANCE_BATCH();
 480
 481    BEGIN_BATCH(5);
 482    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
 483    OUT_BATCH(0);
 484    OUT_BATCH(0);
 485    OUT_BATCH(0);
 486    OUT_BATCH(0);
 487    ADVANCE_BATCH();
 488
 489    BEGIN_BATCH(5);
 490    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 491    OUT_BATCH(0);
 492    OUT_BATCH(0);
 493    OUT_BATCH(0);
 494    OUT_BATCH(0);
 495    ADVANCE_BATCH();
 496 }
 497
 498 static void
 499 gen8_blorp_emit_vf_topology(struct brw_context *brw)
 500 {
 501    BEGIN_BATCH(2);
 502    OUT_BATCH(_3DSTATE_VF_TOPOLOGY << 16 | (2 - 2));
 503    OUT_BATCH(_3DPRIM_RECTLIST);
 504    ADVANCE_BATCH();
 505 }
 506
 507 static void
 508 gen8_blorp_emit_vf_sys_gen_vals_state(struct brw_context *brw)
 509 {
 510    BEGIN_BATCH(2);
 511    OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
 512    OUT_BATCH(0);
 513    ADVANCE_BATCH();
 514 }
 515
 516 static void
 517 gen8_blorp_emit_vf_instancing_state(struct brw_context *brw,
 518                                     unsigned num_elems)
 519 {
 520    for (unsigned i = 0; i < num_elems; ++i) {
 521       BEGIN_BATCH(3);
 522       OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
 523       OUT_BATCH(i);
 524       OUT_BATCH(0);
 525       ADVANCE_BATCH();
 526    }
 527 }
 528
 529 static void
 530 gen8_blorp_emit_vf_state(struct brw_context *brw)
 531 {
 532    BEGIN_BATCH(2);
 533    OUT_BATCH(_3DSTATE_VF << 16 | (2 - 2));
 534    OUT_BATCH(0);
 535    ADVANCE_BATCH();
 536 }
 537
 538 static void
 539 gen8_blorp_emit_depth_stencil_state(struct brw_context *brw,
 540                                     const struct brw_blorp_params *params)
 541 {
 542    const unsigned pkt_len = brw->gen >= 9 ? 4 : 3;
 543
 544    BEGIN_BATCH(pkt_len);
 545    OUT_BATCH(_3DSTATE_WM_DEPTH_STENCIL << 16 | (pkt_len - 2));
 546    OUT_BATCH(0);
 547    OUT_BATCH(0);
 548    if (pkt_len > 3) {
 549       OUT_BATCH(0);
 550    }
 551    ADVANCE_BATCH();
 552 }
 553
 554 static void
 555 gen8_blorp_emit_constant_ps(struct brw_context *brw,
 556                             uint32_t wm_push_const_offset)
 557 {
 558    const int dwords = brw->gen >= 8 ? 11 : 7;
 559    BEGIN_BATCH(dwords);
 560    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (dwords - 2));
 561
 562    if (brw->gen >= 9) {
 563       OUT_BATCH(0);
 564       OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 565    } else {
 566       OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 567       OUT_BATCH(0);
 568    }
 569
 570    if (brw->gen >= 9) {
 571       OUT_BATCH(0);
 572       OUT_BATCH(0);
 573       OUT_BATCH(0);
 574       OUT_BATCH(0);
 575       OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
 576                   wm_push_const_offset);
 577       OUT_BATCH(0);
 578       OUT_BATCH(0);
 579    } else {
 580       OUT_BATCH(wm_push_const_offset);
 581       OUT_BATCH(0);
 582       OUT_BATCH(0);
 583       OUT_BATCH(0);
 584       OUT_BATCH(0);
 585       OUT_BATCH(0);
 586       OUT_BATCH(0);
 587       OUT_BATCH(0);
 588    }
 589
 590    ADVANCE_BATCH();
 591 }
 592
 593 static uint32_t
 594 gen8_blorp_emit_surface_states(struct brw_context *brw,
 595                                const struct brw_blorp_params *params)
 596 {
 597    uint32_t wm_surf_offset_renderbuffer;
 598    uint32_t wm_surf_offset_texture = 0;
 599
 600    intel_miptree_used_for_rendering(params->dst.mt);
 601
 602    wm_surf_offset_renderbuffer =
 603       gen8_blorp_emit_surface_state(brw, &params->dst,
 604                                     I915_GEM_DOMAIN_RENDER,
 605                                     I915_GEM_DOMAIN_RENDER,
 606                                     true /* is_render_target */);
 607    if (params->src.mt) {
 608       const struct brw_blorp_surface_info *surface = &params->src;
 609       struct intel_mipmap_tree *mt = surface->mt;
 610
 611       /* If src is a 2D multisample array texture on Gen7+ using
 612        * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src layer is the
 613        * physical layer holding sample 0.  So, for example, if mt->num_samples
 614        * == 4, then logical layer n corresponds to layer == 4*n.
 615        *
 616        * Multisampled depth and stencil surfaces have the samples interleaved
 617        * (INTEL_MSAA_LAYOUT_IMS) and therefore the layer doesn't need
 618        * adjustment.
 619        */
 620       const unsigned layer_divider =
 621          (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
 622           mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
 623          MAX2(mt->num_samples, 1) : 1;
 624
 625       /* Cube textures are sampled as 2D array. */
 626       const bool is_cube = mt->target == GL_TEXTURE_CUBE_MAP_ARRAY ||
 627                            mt->target == GL_TEXTURE_CUBE_MAP;
 628       const unsigned depth = (is_cube ? 6 : 1) * mt->logical_depth0;
 629       const GLenum target = is_cube ? GL_TEXTURE_2D_ARRAY : mt->target;
 630       const unsigned max_level = surface->level + mt->last_level + 1;
 631       const unsigned layer = mt->target != GL_TEXTURE_3D ?
 632                                 surface->layer / layer_divider : 0;
 633
 634       brw->vtbl.emit_texture_surface_state(brw, mt, target,
 635                                            layer, layer + depth,
 636                                            surface->level, max_level,
 637                                            surface->brw_surfaceformat,
 638                                            surface->swizzle,
 639                                            &wm_surf_offset_texture,
 640                                            -1, false, false);
 641    }
 642
 643    return gen6_blorp_emit_binding_table(brw,
 644                                         wm_surf_offset_renderbuffer,
 645                                         wm_surf_offset_texture);
 646 }
 647
 648 /**
 649  * \copydoc gen6_blorp_exec()
 650  */
 651 void
 652 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
 653 {
 654    uint32_t wm_bind_bo_offset = 0;
 655
 656    if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
 657       brw_upload_state_base_address(brw);
 658
 659    gen7_blorp_emit_cc_viewport(brw);
 660    gen7_l3_state.emit(brw);
 661
 662    gen7_blorp_emit_urb_config(brw);
 663
 664    const uint32_t cc_blend_state_offset =
 665       gen8_blorp_emit_blend_state(brw, params);
 666    gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 667
 668    const uint32_t cc_state_offset = gen6_blorp_emit_cc_state(brw);
 669    gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 670
 671    gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
 672    gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
 673    gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
 674    gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
 675
 676    const uint32_t wm_push_const_offset =
 677       gen6_blorp_emit_wm_constants(brw, params);
 678    gen8_blorp_emit_constant_ps(brw, wm_push_const_offset);
 679    wm_bind_bo_offset = gen8_blorp_emit_surface_states(brw, params);
 680
 681    gen8_blorp_emit_disable_binding_table(brw,
 682                                          _3DSTATE_BINDING_TABLE_POINTERS_VS);
 683    gen8_blorp_emit_disable_binding_table(brw,
 684                                          _3DSTATE_BINDING_TABLE_POINTERS_HS);
 685    gen8_blorp_emit_disable_binding_table(brw,
 686                                          _3DSTATE_BINDING_TABLE_POINTERS_DS);
 687    gen8_blorp_emit_disable_binding_table(brw,
 688                                          _3DSTATE_BINDING_TABLE_POINTERS_GS);
 689
 690    gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 691
 692    if (params->src.mt) {
 693       const uint32_t sampler_offset =
 694          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 695       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 696    }
 697
 698    gen8_emit_3dstate_multisample(brw, params->dst.num_samples);
 699    gen6_emit_3dstate_sample_mask(brw,
 700                                  params->dst.num_samples > 1 ?
 701                                     (1 << params->dst.num_samples) - 1 : 1);
 702
 703    gen8_disable_stages.emit(brw);
 704    gen8_blorp_emit_vs_disable(brw);
 705    gen8_blorp_emit_hs_disable(brw);
 706    gen7_blorp_emit_te_disable(brw);
 707    gen8_blorp_emit_ds_disable(brw);
 708    gen8_blorp_emit_gs_disable(brw);
 709
 710    gen8_blorp_emit_streamout_disable(brw);
 711    gen6_blorp_emit_clip_disable(brw);
 712    gen8_blorp_emit_raster_state(brw);
 713    gen8_blorp_emit_sbe_state(brw, params);
 714    gen8_blorp_emit_sf_config(brw);
 715
 716    gen8_blorp_emit_ps_blend(brw);
 717    gen8_blorp_emit_ps_extra(brw, params);
 718
 719    gen8_blorp_emit_ps_config(brw, params);
 720
 721    gen8_blorp_emit_depth_stencil_state(brw, params);
 722    gen8_blorp_emit_wm_state(brw);
 723
 724    gen8_blorp_emit_depth_disable(brw);
 725    gen7_blorp_emit_clear_params(brw, params);
 726    gen6_blorp_emit_drawing_rectangle(brw, params);
 727    gen8_blorp_emit_vf_topology(brw);
 728    gen8_blorp_emit_vf_sys_gen_vals_state(brw);
 729    gen6_blorp_emit_vertices(brw, params);
 730    gen8_blorp_emit_vf_instancing_state(brw, 2);
 731    gen8_blorp_emit_vf_state(brw);
 732    gen7_blorp_emit_primitive(brw, params);
 733
 734    if (brw->gen < 9)
 735       gen8_write_pma_stall_bits(brw, 0);
 736 }