2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_regions.h"
27 #include "intel_fbo.h"
28 #include "intel_resolve_map.h"
29 #include "brw_context.h"
30 #include "brw_state.h"
31 #include "brw_defines.h"
34 * Helper function to emit depth related command packets.
37 emit_depth_packets(struct brw_context
*brw
,
38 struct intel_mipmap_tree
*depth_mt
,
39 uint32_t depthbuffer_format
,
40 uint32_t depth_surface_type
,
42 struct intel_mipmap_tree
*stencil_mt
,
43 bool stencil_writable
,
44 uint32_t stencil_offset
,
50 uint32_t min_array_element
)
52 intel_emit_depth_stall_flushes(brw
);
54 /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
56 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (8 - 2));
57 OUT_BATCH(depth_surface_type
<< 29 |
58 (depth_writable
? (1 << 28) : 0) |
59 (stencil_mt
!= NULL
&& stencil_writable
) << 27 |
61 depthbuffer_format
<< 18 |
62 (depth_mt
? depth_mt
->region
->pitch
- 1 : 0));
64 OUT_RELOC64(depth_mt
->region
->bo
,
65 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
70 OUT_BATCH(((width
- 1) << 4) | ((height
- 1) << 18) | lod
);
71 OUT_BATCH(((depth
- 1) << 21) | (min_array_element
<< 10));
73 OUT_BATCH(depth_mt
? depth_mt
->qpitch
>> 2 : 0);
78 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
86 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
87 OUT_BATCH(depth_mt
->hiz_mt
->region
->pitch
- 1);
88 OUT_RELOC64(depth_mt
->hiz_mt
->region
->bo
,
89 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
90 OUT_BATCH(depth_mt
->hiz_mt
->qpitch
>> 2);
94 if (stencil_mt
== NULL
) {
96 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
104 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
105 /* The stencil buffer has quirky pitch requirements. From the Graphics
106 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
107 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
108 * field "Surface Pitch":
110 * The pitch must be set to 2x the value computed based on width, as
111 * the stencil buffer is stored with two rows interleaved.
113 * (Note that it is not 100% clear whether this intended to apply to
114 * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
115 * imply that it doesn't), however the comment appears on a "DevIVB+"
116 * page (which would imply that it does). Experiments with the hardware
117 * indicate that it does.
119 OUT_BATCH(HSW_STENCIL_ENABLED
| (2 * stencil_mt
->region
->pitch
- 1));
120 OUT_RELOC64(stencil_mt
->region
->bo
,
121 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
123 OUT_BATCH(stencil_mt
? stencil_mt
->qpitch
>> 2 : 0);
128 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
129 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
134 /* Awful vtable-compatible function; should be cleaned up in the future. */
136 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
137 struct intel_mipmap_tree
*depth_mt
,
138 uint32_t depth_offset
,
139 uint32_t depthbuffer_format
,
140 uint32_t depth_surface_type
,
141 struct intel_mipmap_tree
*stencil_mt
,
142 bool hiz
, bool separate_stencil
,
143 uint32_t width
, uint32_t height
,
144 uint32_t tile_x
, uint32_t tile_y
)
146 struct gl_context
*ctx
= &brw
->ctx
;
147 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
149 unsigned int depth
= 1;
150 unsigned int min_array_element
;
151 GLenum gl_target
= GL_TEXTURE_2D
;
153 const struct intel_mipmap_tree
*mt
= depth_mt
? depth_mt
: stencil_mt
;
154 const struct intel_renderbuffer
*irb
= NULL
;
155 const struct gl_renderbuffer
*rb
= NULL
;
157 irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
159 irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
160 rb
= (struct gl_renderbuffer
*) irb
;
163 depth
= MAX2(rb
->Depth
, 1);
165 gl_target
= rb
->TexImage
->TexObject
->Target
;
169 case GL_TEXTURE_CUBE_MAP_ARRAY
:
170 case GL_TEXTURE_CUBE_MAP
:
171 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
172 * situation, but experiments show that gl_Layer doesn't work when we do
173 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
176 surftype
= BRW_SURFACE_2D
;
180 surftype
= translate_tex_target(gl_target
);
184 if (fb
->MaxNumLayers
> 0 || !irb
) {
185 min_array_element
= 0;
186 } else if (irb
->mt
->num_samples
> 1) {
187 /* Convert physical to logical layer. */
188 min_array_element
= irb
->mt_layer
/ irb
->mt
->num_samples
;
190 min_array_element
= irb
->mt_layer
;
193 lod
= irb
? irb
->mt_level
- irb
->mt
->first_level
: 0;
196 width
= mt
->logical_width0
;
197 height
= mt
->logical_height0
;
200 emit_depth_packets(brw
, depth_mt
, brw_depthbuffer_format(brw
), surftype
,
201 ctx
->Depth
.Mask
!= 0,
202 stencil_mt
, ctx
->Stencil
._WriteEnabled
,
203 brw
->depthstencil
.stencil_offset
,
204 hiz
, width
, height
, depth
, lod
, min_array_element
);
208 * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
210 * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
211 * of the hardware documentation for details.
214 gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
215 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
217 if (op
== GEN6_HIZ_OP_NONE
)
220 assert(mt
->first_level
== 0);
221 assert(mt
->logical_depth0
>= 1);
223 /* The basic algorithm is:
224 * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
225 * 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
226 * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
227 * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
228 * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
229 * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
231 emit_depth_packets(brw
, mt
,
232 brw_depth_format(brw
, mt
->format
),
234 true, /* depth writes */
235 NULL
, false, 0, /* no stencil for now */
241 layer
); /* min_array_element */
243 unsigned rect_width
= minify(mt
->logical_width0
, level
);
244 unsigned rect_height
= minify(mt
->logical_height0
, level
);
247 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
249 OUT_BATCH(((rect_width
- 1) & 0xffff) | ((rect_height
- 1) << 16));
253 /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
254 * resolve or clear operation we want to perform.
259 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
260 dw1
|= GEN8_WM_HZ_DEPTH_RESOLVE
;
262 case GEN6_HIZ_OP_HIZ_RESOLVE
:
263 dw1
|= GEN8_WM_HZ_HIZ_RESOLVE
;
265 case GEN6_HIZ_OP_DEPTH_CLEAR
:
266 dw1
|= GEN8_WM_HZ_DEPTH_CLEAR
;
268 case GEN6_HIZ_OP_NONE
:
269 assert(!"Should not get here.");
272 if (mt
->num_samples
> 0)
273 dw1
|= SET_FIELD(ffs(mt
->num_samples
) - 1, GEN8_WM_HZ_NUM_SAMPLES
);
276 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
279 OUT_BATCH(SET_FIELD(rect_width
, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX
) |
280 SET_FIELD(rect_height
, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX
));
281 OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK
));
284 /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
285 * Data", and no other bits set. This causes 3DSTATE_WM_HZ_OP's state to
286 * take effect, and spawns a rectangle primitive.
288 brw_emit_pipe_control_write(brw
,
289 PIPE_CONTROL_WRITE_IMMEDIATE
,
290 brw
->batch
.workaround_bo
, 0, 0, 0);
292 /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
294 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
301 /* We've clobbered all of the depth packets, and the drawing rectangle,
302 * so we need to ensure those packets are re-emitted before the next
305 * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
307 brw
->state
.dirty
.mesa
|= _NEW_DEPTH
| _NEW_BUFFERS
;