src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "intel_resolve_map.h"
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31 #include "brw_defines.h"
  32
  33 /**
  34  * Helper function to emit depth related command packets.
  35  */
  36 static void
  37 emit_depth_packets(struct brw_context *brw,
  38                    struct intel_mipmap_tree *depth_mt,
  39                    uint32_t depthbuffer_format,
  40                    uint32_t depth_surface_type,
  41                    bool depth_writable,
  42                    struct intel_mipmap_tree *stencil_mt,
  43                    bool stencil_writable,
  44                    uint32_t stencil_offset,
  45                    bool hiz,
  46                    uint32_t width,
  47                    uint32_t height,
  48                    uint32_t depth,
  49                    uint32_t lod,
  50                    uint32_t min_array_element)
  51 {
  52    intel_emit_depth_stall_flushes(brw);
  53
  54    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  55    BEGIN_BATCH(8);
  56    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  57    OUT_BATCH(depth_surface_type << 29 |
  58              (depth_writable ? (1 << 28) : 0) |
  59              (stencil_mt != NULL && stencil_writable) << 27 |
  60              (hiz ? 1 : 0) << 22 |
  61              depthbuffer_format << 18 |
  62              (depth_mt ? depth_mt->region->pitch - 1 : 0));
  63    if (depth_mt) {
  64       OUT_RELOC64(depth_mt->region->bo,
  65                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  66    } else {
  67       OUT_BATCH(0);
  68       OUT_BATCH(0);
  69    }
  70    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  71    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | BDW_MOCS_WB);
  72    OUT_BATCH(0);
  73    OUT_BATCH(depth_mt ? depth_mt->qpitch >> 2 : 0);
  74    ADVANCE_BATCH();
  75
  76    if (!hiz) {
  77       BEGIN_BATCH(5);
  78       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  79       OUT_BATCH(0);
  80       OUT_BATCH(0);
  81       OUT_BATCH(0);
  82       OUT_BATCH(0);
  83       ADVANCE_BATCH();
  84    } else {
  85       BEGIN_BATCH(5);
  86       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  87       OUT_BATCH((depth_mt->hiz_mt->region->pitch - 1) | BDW_MOCS_WB << 25);
  88       OUT_RELOC64(depth_mt->hiz_mt->region->bo,
  89                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  90       OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2);
  91       ADVANCE_BATCH();
  92    }
  93
  94    if (stencil_mt == NULL) {
  95       BEGIN_BATCH(5);
  96       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
  97       OUT_BATCH(0);
  98       OUT_BATCH(0);
  99       OUT_BATCH(0);
 100       OUT_BATCH(0);
 101       ADVANCE_BATCH();
 102    } else {
 103       BEGIN_BATCH(5);
 104       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 105       /* The stencil buffer has quirky pitch requirements.  From the Graphics
 106        * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
 107        * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
 108        * field "Surface Pitch":
 109        *
 110        *    The pitch must be set to 2x the value computed based on width, as
 111        *    the stencil buffer is stored with two rows interleaved.
 112        *
 113        * (Note that it is not 100% clear whether this intended to apply to
 114        * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
 115        * imply that it doesn't), however the comment appears on a "DevIVB+"
 116        * page (which would imply that it does).  Experiments with the hardware
 117        * indicate that it does.
 118        */
 119       OUT_BATCH(HSW_STENCIL_ENABLED | BDW_MOCS_WB << 22 |
 120                 (2 * stencil_mt->region->pitch - 1));
 121       OUT_RELOC64(stencil_mt->region->bo,
 122                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 123                   stencil_offset);
 124       OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
 125       ADVANCE_BATCH();
 126    }
 127
 128    BEGIN_BATCH(3);
 129    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 130    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 131    OUT_BATCH(1);
 132    ADVANCE_BATCH();
 133 }
 134
 135 /* Awful vtable-compatible function; should be cleaned up in the future. */
 136 void
 137 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 138                             struct intel_mipmap_tree *depth_mt,
 139                             uint32_t depth_offset,
 140                             uint32_t depthbuffer_format,
 141                             uint32_t depth_surface_type,
 142                             struct intel_mipmap_tree *stencil_mt,
 143                             bool hiz, bool separate_stencil,
 144                             uint32_t width, uint32_t height,
 145                             uint32_t tile_x, uint32_t tile_y)
 146 {
 147    struct gl_context *ctx = &brw->ctx;
 148    struct gl_framebuffer *fb = ctx->DrawBuffer;
 149    uint32_t surftype;
 150    unsigned int depth = 1;
 151    unsigned int min_array_element;
 152    GLenum gl_target = GL_TEXTURE_2D;
 153    unsigned int lod;
 154    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 155    const struct intel_renderbuffer *irb = NULL;
 156    const struct gl_renderbuffer *rb = NULL;
 157
 158    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 159    if (!irb)
 160       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 161    rb = (struct gl_renderbuffer *) irb;
 162
 163    if (rb) {
 164       depth = MAX2(rb->Depth, 1);
 165       if (rb->TexImage)
 166          gl_target = rb->TexImage->TexObject->Target;
 167    }
 168
 169    switch (gl_target) {
 170    case GL_TEXTURE_CUBE_MAP_ARRAY:
 171    case GL_TEXTURE_CUBE_MAP:
 172       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 173        * situation, but experiments show that gl_Layer doesn't work when we do
 174        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 175        * equivalent.
 176        */
 177       surftype = BRW_SURFACE_2D;
 178       depth *= 6;
 179       break;
 180    default:
 181       surftype = translate_tex_target(gl_target);
 182       break;
 183    }
 184
 185    if (fb->MaxNumLayers > 0 || !irb) {
 186       min_array_element = 0;
 187    } else if (irb->mt->num_samples > 1) {
 188       /* Convert physical to logical layer. */
 189       min_array_element = irb->mt_layer / irb->mt->num_samples;
 190    } else {
 191       min_array_element = irb->mt_layer;
 192    }
 193
 194    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 195
 196    if (mt) {
 197       width = mt->logical_width0;
 198       height = mt->logical_height0;
 199    }
 200
 201    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 202                       ctx->Depth.Mask != 0,
 203                       stencil_mt, ctx->Stencil._WriteEnabled,
 204                       brw->depthstencil.stencil_offset,
 205                       hiz, width, height, depth, lod, min_array_element);
 206 }
 207
 208 /**
 209  * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
 210  *
 211  * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
 212  * of the hardware documentation for details.
 213  */
 214 void
 215 gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 216               unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 217 {
 218    if (op == GEN6_HIZ_OP_NONE)
 219       return;
 220
 221    assert(mt->first_level == 0);
 222    assert(mt->logical_depth0 >= 1);
 223
 224    /* The basic algorithm is:
 225     * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
 226     *   3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
 227     * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
 228     * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
 229     * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
 230     * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
 231     */
 232    emit_depth_packets(brw, mt,
 233                       brw_depth_format(brw, mt->format),
 234                       BRW_SURFACE_2D,
 235                       true, /* depth writes */
 236                       NULL, false, 0, /* no stencil for now */
 237                       true, /* hiz */
 238                       mt->logical_width0,
 239                       mt->logical_height0,
 240                       mt->logical_depth0,
 241                       level,
 242                       layer); /* min_array_element */
 243
 244    unsigned rect_width = minify(mt->logical_width0, level);
 245    unsigned rect_height = minify(mt->logical_height0, level);
 246
 247    BEGIN_BATCH(4);
 248    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 249    OUT_BATCH(0);
 250    OUT_BATCH(((rect_width - 1) & 0xffff) | ((rect_height - 1) << 16));
 251    OUT_BATCH(0);
 252    ADVANCE_BATCH();
 253
 254    /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
 255     * resolve or clear operation we want to perform.
 256     */
 257    uint32_t dw1 = 0;
 258
 259    switch (op) {
 260    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 261       dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE;
 262       break;
 263    case GEN6_HIZ_OP_HIZ_RESOLVE:
 264       dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
 265       break;
 266    case GEN6_HIZ_OP_DEPTH_CLEAR:
 267       dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
 268       break;
 269    case GEN6_HIZ_OP_NONE:
 270       assert(!"Should not get here.");
 271    }
 272
 273    if (mt->num_samples > 0)
 274       dw1 |= SET_FIELD(ffs(mt->num_samples) - 1, GEN8_WM_HZ_NUM_SAMPLES);
 275
 276    BEGIN_BATCH(5);
 277    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 278    OUT_BATCH(dw1);
 279    OUT_BATCH(0);
 280    OUT_BATCH(SET_FIELD(rect_width, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX) |
 281              SET_FIELD(rect_height, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX));
 282    OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK));
 283    ADVANCE_BATCH();
 284
 285    /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
 286     * Data", and no other bits set.  This causes 3DSTATE_WM_HZ_OP's state to
 287     * take effect, and spawns a rectangle primitive.
 288     */
 289    brw_emit_pipe_control_write(brw,
 290                                PIPE_CONTROL_WRITE_IMMEDIATE,
 291                                brw->batch.workaround_bo, 0, 0, 0);
 292
 293    /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
 294    BEGIN_BATCH(5);
 295    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    OUT_BATCH(0);
 300    ADVANCE_BATCH();
 301
 302    /* We've clobbered all of the depth packets, and the drawing rectangle,
 303     * so we need to ensure those packets are re-emitted before the next
 304     * primitive.
 305     *
 306     * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
 307     */
 308    brw->state.dirty.mesa |= _NEW_DEPTH | _NEW_BUFFERS;
 309 }