2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_fbo.h"
27 #include "intel_resolve_map.h"
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
34 * Helper function to emit depth related command packets.
37 emit_depth_packets(struct brw_context
*brw
,
38 struct intel_mipmap_tree
*depth_mt
,
39 uint32_t depthbuffer_format
,
40 uint32_t depth_surface_type
,
42 struct intel_mipmap_tree
*stencil_mt
,
43 bool stencil_writable
,
44 uint32_t stencil_offset
,
50 uint32_t min_array_element
)
52 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
54 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
55 if (!depth_mt
&& !stencil_mt
&& brw
->no_depth_or_stencil
) {
60 intel_emit_depth_stall_flushes(brw
);
62 /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
64 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (8 - 2));
65 OUT_BATCH(depth_surface_type
<< 29 |
66 (depth_writable
? (1 << 28) : 0) |
67 (stencil_mt
!= NULL
&& stencil_writable
) << 27 |
69 depthbuffer_format
<< 18 |
70 (depth_mt
? depth_mt
->pitch
- 1 : 0));
72 OUT_RELOC64(depth_mt
->bo
,
73 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
78 OUT_BATCH(((width
- 1) << 4) | ((height
- 1) << 18) | lod
);
79 OUT_BATCH(((depth
- 1) << 21) | (min_array_element
<< 10) | mocs_wb
);
81 OUT_BATCH(((depth
- 1) << 21) | (depth_mt
? depth_mt
->qpitch
>> 2 : 0));
86 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
94 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
95 OUT_BATCH((depth_mt
->hiz_mt
->pitch
- 1) | mocs_wb
<< 25);
96 OUT_RELOC64(depth_mt
->hiz_mt
->bo
,
97 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
98 OUT_BATCH(depth_mt
->hiz_mt
->qpitch
>> 2);
102 if (stencil_mt
== NULL
) {
104 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
112 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
113 /* The stencil buffer has quirky pitch requirements. From the Graphics
114 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
115 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
116 * field "Surface Pitch":
118 * The pitch must be set to 2x the value computed based on width, as
119 * the stencil buffer is stored with two rows interleaved.
121 * (Note that it is not 100% clear whether this intended to apply to
122 * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
123 * imply that it doesn't), however the comment appears on a "DevIVB+"
124 * page (which would imply that it does). Experiments with the hardware
125 * indicate that it does.
127 OUT_BATCH(HSW_STENCIL_ENABLED
| mocs_wb
<< 22 |
128 (2 * stencil_mt
->pitch
- 1));
129 OUT_RELOC64(stencil_mt
->bo
,
130 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
132 OUT_BATCH(stencil_mt
? stencil_mt
->qpitch
>> 2 : 0);
137 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
138 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
142 brw
->no_depth_or_stencil
= !depth_mt
&& !stencil_mt
;
145 /* Awful vtable-compatible function; should be cleaned up in the future. */
147 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
148 struct intel_mipmap_tree
*depth_mt
,
149 uint32_t depth_offset
,
150 uint32_t depthbuffer_format
,
151 uint32_t depth_surface_type
,
152 struct intel_mipmap_tree
*stencil_mt
,
153 bool hiz
, bool separate_stencil
,
154 uint32_t width
, uint32_t height
,
155 uint32_t tile_x
, uint32_t tile_y
)
157 struct gl_context
*ctx
= &brw
->ctx
;
158 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
160 unsigned int depth
= 1;
161 unsigned int min_array_element
;
162 GLenum gl_target
= GL_TEXTURE_2D
;
164 const struct intel_mipmap_tree
*mt
= depth_mt
? depth_mt
: stencil_mt
;
165 const struct intel_renderbuffer
*irb
= NULL
;
166 const struct gl_renderbuffer
*rb
= NULL
;
168 irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
170 irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
171 rb
= (struct gl_renderbuffer
*) irb
;
174 depth
= MAX2(irb
->layer_count
, 1);
176 gl_target
= rb
->TexImage
->TexObject
->Target
;
180 case GL_TEXTURE_CUBE_MAP_ARRAY
:
181 case GL_TEXTURE_CUBE_MAP
:
182 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
183 * situation, but experiments show that gl_Layer doesn't work when we do
184 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
187 surftype
= BRW_SURFACE_2D
;
192 depth
= MAX2(mt
->logical_depth0
, 1);
195 surftype
= translate_tex_target(gl_target
);
199 min_array_element
= irb
? irb
->mt_layer
: 0;
201 lod
= irb
? irb
->mt_level
- irb
->mt
->first_level
: 0;
204 width
= mt
->logical_width0
;
205 height
= mt
->logical_height0
;
208 emit_depth_packets(brw
, depth_mt
, brw_depthbuffer_format(brw
), surftype
,
209 ctx
->Depth
.Mask
!= 0,
210 stencil_mt
, ctx
->Stencil
._WriteEnabled
,
211 brw
->depthstencil
.stencil_offset
,
212 hiz
, width
, height
, depth
, lod
, min_array_element
);
216 * Should we set the PMA FIX ENABLE bit?
218 * To avoid unnecessary depth related stalls, we need to set this bit.
219 * However, there is a very complicated formula which governs when it
220 * is legal to do so. This function computes that.
222 * See the documenation for the CACHE_MODE_1 register, bit 11.
225 pma_fix_enable(const struct brw_context
*brw
)
227 const struct gl_context
*ctx
= &brw
->ctx
;
228 /* BRW_NEW_FRAGMENT_PROGRAM */
229 const struct gl_fragment_program
*fp
= brw
->fragment_program
;
231 struct intel_renderbuffer
*depth_irb
=
232 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
234 /* 3DSTATE_WM::ForceThreadDispatch is never used. */
235 const bool wm_force_thread_dispatch
= false;
237 /* 3DSTATE_RASTER::ForceSampleCount is never used. */
238 const bool raster_force_sample_count_nonzero
= false;
241 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
242 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
244 const bool hiz_enabled
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
246 /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
247 * We always leave this set to EDSC_NORMAL (0).
249 const bool edsc_not_preps
= true;
251 /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
252 const bool pixel_shader_valid
= true;
254 /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
255 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
256 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
257 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
259 * HiZ operations are done outside of the normal state upload, so they're
260 * definitely not happening now.
262 const bool in_hiz_op
= false;
265 * DEPTH_STENCIL_STATE::DepthTestEnable
267 const bool depth_test_enabled
= depth_irb
&& ctx
->Depth
.Test
;
270 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
271 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
273 const bool depth_writes_enabled
= ctx
->Depth
.Mask
;
276 * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
277 * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
278 * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
280 const bool stencil_writes_enabled
= ctx
->Stencil
._WriteEnabled
;
282 /* BRW_NEW_FRAGMENT_PROGRAM:
283 * 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode == PSCDEPTH_OFF
285 const bool ps_computes_depth
=
286 (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) &&
287 fp
->FragDepthLayout
!= FRAG_DEPTH_LAYOUT_UNCHANGED
;
289 /* CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
290 * CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
291 * _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
292 * _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
294 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
295 * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
297 const bool kill_pixel
=
298 brw
->wm
.prog_data
->uses_kill
||
299 brw
->wm
.prog_data
->uses_omask
||
300 (ctx
->Multisample
._Enabled
&& ctx
->Multisample
.SampleAlphaToCoverage
) ||
301 ctx
->Color
.AlphaEnabled
;
303 /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
304 return !wm_force_thread_dispatch
&&
305 !raster_force_sample_count_nonzero
&&
308 pixel_shader_valid
&&
310 depth_test_enabled
&&
311 (ps_computes_depth
||
312 (kill_pixel
&& (depth_writes_enabled
|| stencil_writes_enabled
)));
316 write_pma_stall_bits(struct brw_context
*brw
, uint32_t pma_stall_bits
)
318 struct gl_context
*ctx
= &brw
->ctx
;
320 /* If we haven't actually changed the value, bail now to avoid unnecessary
321 * pipeline stalls and register writes.
323 if (brw
->pma_stall_bits
== pma_stall_bits
)
326 brw
->pma_stall_bits
= pma_stall_bits
;
328 /* According to the PIPE_CONTROL documentation, software should emit a
329 * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
330 * to the LRI. If stencil buffer writes are enabled, then a Render Cache
331 * Flush is also necessary.
333 const uint32_t render_cache_flush
=
334 ctx
->Stencil
._WriteEnabled
? PIPE_CONTROL_WRITE_FLUSH
: 0;
335 brw_emit_pipe_control_flush(brw
,
336 PIPE_CONTROL_CS_STALL
|
337 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
340 /* CACHE_MODE_1 is a non-privileged register. */
342 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
343 OUT_BATCH(GEN7_CACHE_MODE_1
);
344 OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS
| pma_stall_bits
);
347 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
348 * Flush bits is often necessary. We do it regardless because it's easier.
349 * The render cache flush is also necessary if stencil writes are enabled.
351 brw_emit_pipe_control_flush(brw
,
352 PIPE_CONTROL_DEPTH_STALL
|
353 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
359 gen8_emit_pma_stall_workaround(struct brw_context
*brw
)
362 if (pma_fix_enable(brw
))
363 bits
|= GEN8_HIZ_NP_PMA_FIX_ENABLE
| GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE
;
365 write_pma_stall_bits(brw
, bits
);
368 const struct brw_tracked_state gen8_pma_fix
= {
370 .mesa
= _NEW_BUFFERS
|
375 .brw
= BRW_NEW_FRAGMENT_PROGRAM
,
376 .cache
= CACHE_NEW_WM_PROG
,
378 .emit
= gen8_emit_pma_stall_workaround
382 * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
384 * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
385 * of the hardware documentation for details.
388 gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
389 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
391 if (op
== GEN6_HIZ_OP_NONE
)
394 /* Disable the PMA stall fix since we're about to do a HiZ operation. */
395 write_pma_stall_bits(brw
, 0);
397 assert(mt
->first_level
== 0);
398 assert(mt
->logical_depth0
>= 1);
400 /* If we're operating on LOD 0, align to 8x4 to meet the alignment
401 * requirements for most HiZ operations. Otherwise, use the actual size
402 * to allow the hardware to calculate the miplevel offsets correctly.
404 uint32_t surface_width
= ALIGN(mt
->logical_width0
, level
== 0 ? 8 : 1);
405 uint32_t surface_height
= ALIGN(mt
->logical_height0
, level
== 0 ? 4 : 1);
407 /* The basic algorithm is:
408 * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
409 * 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
410 * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
411 * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
412 * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
413 * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
415 emit_depth_packets(brw
, mt
,
416 brw_depth_format(brw
, mt
->format
),
418 true, /* depth writes */
419 NULL
, false, 0, /* no stencil for now */
425 layer
); /* min_array_element */
427 /* Depth buffer clears and HiZ resolves must use an 8x4 aligned rectangle.
428 * Note that intel_miptree_level_enable_hiz disables HiZ for miplevels > 0
429 * which aren't 8x4 aligned, so expanding the size is safe - it'll just
430 * draw into empty padding space.
432 unsigned rect_width
= ALIGN(minify(mt
->logical_width0
, level
), 8);
433 unsigned rect_height
= ALIGN(minify(mt
->logical_height0
, level
), 4);
436 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
438 OUT_BATCH(((rect_width
- 1) & 0xffff) | ((rect_height
- 1) << 16));
442 /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
443 * resolve or clear operation we want to perform.
448 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
449 dw1
|= GEN8_WM_HZ_DEPTH_RESOLVE
;
451 case GEN6_HIZ_OP_HIZ_RESOLVE
:
452 dw1
|= GEN8_WM_HZ_HIZ_RESOLVE
;
454 case GEN6_HIZ_OP_DEPTH_CLEAR
:
455 dw1
|= GEN8_WM_HZ_DEPTH_CLEAR
;
457 case GEN6_HIZ_OP_NONE
:
458 unreachable("Should not get here.");
461 if (mt
->num_samples
> 0)
462 dw1
|= SET_FIELD(ffs(mt
->num_samples
) - 1, GEN8_WM_HZ_NUM_SAMPLES
);
465 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
468 OUT_BATCH(SET_FIELD(rect_width
, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX
) |
469 SET_FIELD(rect_height
, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX
));
470 OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK
));
473 /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
474 * Data", and no other bits set. This causes 3DSTATE_WM_HZ_OP's state to
475 * take effect, and spawns a rectangle primitive.
477 brw_emit_pipe_control_write(brw
,
478 PIPE_CONTROL_WRITE_IMMEDIATE
,
479 brw
->batch
.workaround_bo
, 0, 0, 0);
481 /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
483 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
490 /* Mark this buffer as needing a TC flush, as we've rendered to it. */
491 brw_render_cache_set_add_bo(brw
, mt
->bo
);
493 /* We've clobbered all of the depth packets, and the drawing rectangle,
494 * so we need to ensure those packets are re-emitted before the next
497 * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
499 brw
->state
.dirty
.mesa
|= _NEW_DEPTH
| _NEW_BUFFERS
;