src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_fbo.h"
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30 #include "compiler/brw_eu_defines.h"
  31 #include "brw_wm.h"
  32 #include "main/framebuffer.h"
  33
  34 /**
  35  * Helper function to emit depth related command packets.
  36  */
  37 static void
  38 emit_depth_packets(struct brw_context *brw,
  39                    struct intel_mipmap_tree *depth_mt,
  40                    uint32_t depthbuffer_format,
  41                    uint32_t depth_surface_type,
  42                    struct intel_mipmap_tree *stencil_mt,
  43                    bool hiz,
  44                    uint32_t width,
  45                    uint32_t height,
  46                    uint32_t depth,
  47                    uint32_t lod,
  48                    uint32_t min_array_element)
  49 {
  50    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  51    uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  52
  53    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
  54    if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
  55       assert(brw->hw_ctx);
  56       return;
  57    }
  58
  59    brw_emit_depth_stall_flushes(brw);
  60
  61    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  62    BEGIN_BATCH(8);
  63    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  64    OUT_BATCH(depth_surface_type << 29 |
  65              (depth_mt != NULL) << 28 | /* Depth Write Enable */
  66              (stencil_mt != NULL) << 27 | /* Stencil Write Enable */
  67              (hiz ? 1 : 0) << 22 |
  68              depthbuffer_format << 18 |
  69              (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
  70    if (depth_mt) {
  71       OUT_RELOC64(depth_mt->bo, RELOC_WRITE, 0);
  72    } else {
  73       OUT_BATCH(0);
  74       OUT_BATCH(0);
  75    }
  76    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  77    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
  78    OUT_BATCH(0);
  79    OUT_BATCH(((depth - 1) << 21) |
  80               (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
  81    ADVANCE_BATCH();
  82
  83    if (stencil_mt == NULL) {
  84       BEGIN_BATCH(5);
  85       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
  86       OUT_BATCH(0);
  87       OUT_BATCH(0);
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90       ADVANCE_BATCH();
  91    } else {
  92       BEGIN_BATCH(5);
  93       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
  94       OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
  95                 (stencil_mt->surf.row_pitch - 1));
  96       OUT_RELOC64(stencil_mt->bo, RELOC_WRITE, 0);
  97       OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
  98       ADVANCE_BATCH();
  99    }
 100
 101    if (!hiz) {
 102       BEGIN_BATCH(5);
 103       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
 104       OUT_BATCH(0);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       ADVANCE_BATCH();
 109    } else {
 110       assert(depth_mt);
 111       BEGIN_BATCH(5);
 112       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
 113       OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25);
 114       OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
 115       OUT_BATCH(depth_mt->aux_buf->qpitch >> 2);
 116       ADVANCE_BATCH();
 117    }
 118
 119    BEGIN_BATCH(3);
 120    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 121    OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);
 122    OUT_BATCH(1);
 123    ADVANCE_BATCH();
 124
 125    brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 126 }
 127
 128 /* Awful vtable-compatible function; should be cleaned up in the future. */
 129 void
 130 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 131                             struct intel_mipmap_tree *depth_mt,
 132                             uint32_t depth_offset,
 133                             uint32_t depthbuffer_format,
 134                             uint32_t depth_surface_type,
 135                             struct intel_mipmap_tree *stencil_mt,
 136                             bool hiz, bool separate_stencil,
 137                             uint32_t width, uint32_t height,
 138                             uint32_t tile_x, uint32_t tile_y)
 139 {
 140    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 141    struct gl_context *ctx = &brw->ctx;
 142    struct gl_framebuffer *fb = ctx->DrawBuffer;
 143    uint32_t surftype;
 144    unsigned int depth = 1;
 145    unsigned int min_array_element;
 146    GLenum gl_target = GL_TEXTURE_2D;
 147    unsigned int lod;
 148    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 149    const struct intel_renderbuffer *irb = NULL;
 150    const struct gl_renderbuffer *rb = NULL;
 151
 152    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 153    if (!irb)
 154       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 155    rb = (struct gl_renderbuffer *) irb;
 156
 157    if (rb) {
 158       depth = MAX2(irb->layer_count, 1);
 159       if (rb->TexImage)
 160          gl_target = rb->TexImage->TexObject->Target;
 161    }
 162
 163    switch (gl_target) {
 164    case GL_TEXTURE_CUBE_MAP_ARRAY:
 165    case GL_TEXTURE_CUBE_MAP:
 166       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 167        * situation, but experiments show that gl_Layer doesn't work when we do
 168        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 169        * equivalent.
 170        */
 171       surftype = BRW_SURFACE_2D;
 172       depth *= 6;
 173       break;
 174    case GL_TEXTURE_3D:
 175       assert(mt);
 176       depth = mt->surf.logical_level0_px.depth;
 177       surftype = translate_tex_target(gl_target);
 178       break;
 179    case GL_TEXTURE_1D_ARRAY:
 180    case GL_TEXTURE_1D:
 181       if (devinfo->gen >= 9) {
 182          /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
 183           * textures but it does allow pretending it's a 2D texture
 184           * instead.
 185           */
 186          surftype = BRW_SURFACE_2D;
 187          break;
 188       }
 189       /* fallthrough */
 190    default:
 191       surftype = translate_tex_target(gl_target);
 192       break;
 193    }
 194
 195    min_array_element = irb ? irb->mt_layer : 0;
 196
 197    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 198
 199    if (mt) {
 200       width = mt->surf.logical_level0_px.width;
 201       height = mt->surf.logical_level0_px.height;
 202    }
 203
 204    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 205                       stencil_mt,
 206                       hiz, width, height, depth, lod, min_array_element);
 207 }
 208
 209 /**
 210  * Should we set the PMA FIX ENABLE bit?
 211  *
 212  * To avoid unnecessary depth related stalls, we need to set this bit.
 213  * However, there is a very complicated formula which governs when it
 214  * is legal to do so.  This function computes that.
 215  *
 216  * See the documenation for the CACHE_MODE_1 register, bit 11.
 217  */
 218 static bool
 219 pma_fix_enable(const struct brw_context *brw)
 220 {
 221    const struct gl_context *ctx = &brw->ctx;
 222    /* BRW_NEW_FS_PROG_DATA */
 223    const struct brw_wm_prog_data *wm_prog_data =
 224       brw_wm_prog_data(brw->wm.base.prog_data);
 225    /* _NEW_BUFFERS */
 226    struct intel_renderbuffer *depth_irb =
 227       intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 228
 229    /* 3DSTATE_WM::ForceThreadDispatch is never used. */
 230    const bool wm_force_thread_dispatch = false;
 231
 232    /* 3DSTATE_RASTER::ForceSampleCount is never used. */
 233    const bool raster_force_sample_count_nonzero = false;
 234
 235    /* _NEW_BUFFERS:
 236     * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 237     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 238     */
 239    const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
 240
 241    /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
 242    const bool edsc_not_preps = !wm_prog_data->early_fragment_tests;
 243
 244    /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
 245    const bool pixel_shader_valid = true;
 246
 247    /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 248     *   3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 249     *   3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 250     *   3DSTATE_WM_HZ_OP::StencilBufferClear)
 251     *
 252     * HiZ operations are done outside of the normal state upload, so they're
 253     * definitely not happening now.
 254     */
 255    const bool in_hiz_op = false;
 256
 257    /* _NEW_DEPTH:
 258     * DEPTH_STENCIL_STATE::DepthTestEnable
 259     */
 260    const bool depth_test_enabled = depth_irb && ctx->Depth.Test;
 261
 262    /* _NEW_DEPTH:
 263     * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 264     * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
 265     */
 266    const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
 267
 268    /* _NEW_STENCIL:
 269     * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
 270     * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
 271     * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
 272     */
 273    const bool stencil_writes_enabled = brw->stencil_write_enabled;
 274
 275    /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
 276    const bool ps_computes_depth =
 277       wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
 278
 279    /* BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::PixelShaderKillsPixels
 280     * BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::oMask Present to RenderTarget
 281     * _NEW_MULTISAMPLE:         3DSTATE_PS_BLEND::AlphaToCoverageEnable
 282     * _NEW_COLOR:               3DSTATE_PS_BLEND::AlphaTestEnable
 283     * _NEW_BUFFERS:             3DSTATE_PS_BLEND::AlphaTestEnable
 284     *                           3DSTATE_PS_BLEND::AlphaToCoverageEnable
 285     *
 286     * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
 287     * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
 288     */
 289    const bool kill_pixel =
 290       wm_prog_data->uses_kill ||
 291       wm_prog_data->uses_omask ||
 292       _mesa_is_alpha_test_enabled(ctx) ||
 293       _mesa_is_alpha_to_coverage_enabled(ctx);
 294
 295    /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
 296    return !wm_force_thread_dispatch &&
 297           !raster_force_sample_count_nonzero &&
 298           hiz_enabled &&
 299           edsc_not_preps &&
 300           pixel_shader_valid &&
 301           !in_hiz_op &&
 302           depth_test_enabled &&
 303           (ps_computes_depth ||
 304            (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
 305 }
 306
 307 void
 308 gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 309 {
 310    /* If we haven't actually changed the value, bail now to avoid unnecessary
 311     * pipeline stalls and register writes.
 312     */
 313    if (brw->pma_stall_bits == pma_stall_bits)
 314       return;
 315
 316    brw->pma_stall_bits = pma_stall_bits;
 317
 318    /* According to the PIPE_CONTROL documentation, software should emit a
 319     * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
 320     * to the LRI.  If stencil buffer writes are enabled, then a Render Cache
 321     * Flush is also necessary.
 322     */
 323    const uint32_t render_cache_flush =
 324       brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
 325    brw_emit_pipe_control_flush(brw,
 326                                PIPE_CONTROL_CS_STALL |
 327                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 328                                render_cache_flush);
 329
 330    /* CACHE_MODE_1 is a non-privileged register. */
 331    brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
 332                            GEN8_HIZ_PMA_MASK_BITS |
 333                            pma_stall_bits );
 334
 335    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 336     * Flush bits is often necessary.  We do it regardless because it's easier.
 337     * The render cache flush is also necessary if stencil writes are enabled.
 338     */
 339    brw_emit_pipe_control_flush(brw,
 340                                PIPE_CONTROL_DEPTH_STALL |
 341                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 342                                render_cache_flush);
 343
 344 }
 345
 346 static void
 347 gen8_emit_pma_stall_workaround(struct brw_context *brw)
 348 {
 349    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 350    uint32_t bits = 0;
 351
 352    if (devinfo->gen >= 9)
 353       return;
 354
 355    if (pma_fix_enable(brw))
 356       bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
 357
 358    gen8_write_pma_stall_bits(brw, bits);
 359 }
 360
 361 const struct brw_tracked_state gen8_pma_fix = {
 362    .dirty = {
 363       .mesa = _NEW_BUFFERS |
 364               _NEW_COLOR |
 365               _NEW_DEPTH |
 366               _NEW_MULTISAMPLE |
 367               _NEW_STENCIL,
 368       .brw = BRW_NEW_BLORP |
 369              BRW_NEW_FS_PROG_DATA,
 370    },
 371    .emit = gen8_emit_pma_stall_workaround
 372 };