src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_fbo.h"
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30 #include "compiler/brw_eu_defines.h"
  31 #include "brw_wm.h"
  32 #include "main/framebuffer.h"
  33
  34 /**
  35  * Helper function to emit depth related command packets.
  36  */
  37 static void
  38 emit_depth_packets(struct brw_context *brw,
  39                    struct intel_mipmap_tree *depth_mt,
  40                    uint32_t depthbuffer_format,
  41                    uint32_t depth_surface_type,
  42                    bool depth_writable,
  43                    struct intel_mipmap_tree *stencil_mt,
  44                    bool stencil_writable,
  45                    bool hiz,
  46                    uint32_t width,
  47                    uint32_t height,
  48                    uint32_t depth,
  49                    uint32_t lod,
  50                    uint32_t min_array_element)
  51 {
  52    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  53
  54    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
  55    if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
  56       assert(brw->hw_ctx);
  57       return;
  58    }
  59
  60    brw_emit_depth_stall_flushes(brw);
  61
  62    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  63    BEGIN_BATCH(8);
  64    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  65    OUT_BATCH(depth_surface_type << 29 |
  66              (depth_writable ? (1 << 28) : 0) |
  67              (stencil_mt != NULL && stencil_writable) << 27 |
  68              (hiz ? 1 : 0) << 22 |
  69              depthbuffer_format << 18 |
  70              (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
  71    if (depth_mt) {
  72       OUT_RELOC64(depth_mt->bo, RELOC_WRITE, 0);
  73    } else {
  74       OUT_BATCH(0);
  75       OUT_BATCH(0);
  76    }
  77    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  78    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
  79    OUT_BATCH(0);
  80    OUT_BATCH(((depth - 1) << 21) |
  81               (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
  82    ADVANCE_BATCH();
  83
  84    if (!hiz) {
  85       BEGIN_BATCH(5);
  86       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  87       OUT_BATCH(0);
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90       OUT_BATCH(0);
  91       ADVANCE_BATCH();
  92    } else {
  93       assert(depth_mt);
  94       BEGIN_BATCH(5);
  95       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  96       OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
  97       OUT_RELOC64(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
  98       OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
  99       ADVANCE_BATCH();
 100    }
 101
 102    if (stencil_mt == NULL) {
 103       BEGIN_BATCH(5);
 104       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       ADVANCE_BATCH();
 110    } else {
 111       BEGIN_BATCH(5);
 112       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 113       OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
 114                 (stencil_mt->surf.row_pitch - 1));
 115       OUT_RELOC64(stencil_mt->bo, RELOC_WRITE, 0);
 116       OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
 117       ADVANCE_BATCH();
 118    }
 119
 120    BEGIN_BATCH(3);
 121    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 122    OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);
 123    OUT_BATCH(1);
 124    ADVANCE_BATCH();
 125
 126    brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 127 }
 128
 129 /* Awful vtable-compatible function; should be cleaned up in the future. */
 130 void
 131 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 132                             struct intel_mipmap_tree *depth_mt,
 133                             uint32_t depth_offset,
 134                             uint32_t depthbuffer_format,
 135                             uint32_t depth_surface_type,
 136                             struct intel_mipmap_tree *stencil_mt,
 137                             bool hiz, bool separate_stencil,
 138                             uint32_t width, uint32_t height,
 139                             uint32_t tile_x, uint32_t tile_y)
 140 {
 141    struct gl_context *ctx = &brw->ctx;
 142    struct gl_framebuffer *fb = ctx->DrawBuffer;
 143    uint32_t surftype;
 144    unsigned int depth = 1;
 145    unsigned int min_array_element;
 146    GLenum gl_target = GL_TEXTURE_2D;
 147    unsigned int lod;
 148    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 149    const struct intel_renderbuffer *irb = NULL;
 150    const struct gl_renderbuffer *rb = NULL;
 151
 152    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 153    if (!irb)
 154       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 155    rb = (struct gl_renderbuffer *) irb;
 156
 157    if (rb) {
 158       depth = MAX2(irb->layer_count, 1);
 159       if (rb->TexImage)
 160          gl_target = rb->TexImage->TexObject->Target;
 161    }
 162
 163    switch (gl_target) {
 164    case GL_TEXTURE_CUBE_MAP_ARRAY:
 165    case GL_TEXTURE_CUBE_MAP:
 166       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 167        * situation, but experiments show that gl_Layer doesn't work when we do
 168        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 169        * equivalent.
 170        */
 171       surftype = BRW_SURFACE_2D;
 172       depth *= 6;
 173       break;
 174    case GL_TEXTURE_3D:
 175       assert(mt);
 176       depth = mt->surf.logical_level0_px.depth;
 177       surftype = translate_tex_target(gl_target);
 178       break;
 179    case GL_TEXTURE_1D_ARRAY:
 180    case GL_TEXTURE_1D:
 181       if (brw->gen >= 9) {
 182          /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
 183           * textures but it does allow pretending it's a 2D texture
 184           * instead.
 185           */
 186          surftype = BRW_SURFACE_2D;
 187          break;
 188       }
 189       /* fallthrough */
 190    default:
 191       surftype = translate_tex_target(gl_target);
 192       break;
 193    }
 194
 195    min_array_element = irb ? irb->mt_layer : 0;
 196
 197    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 198
 199    if (mt) {
 200       width = mt->surf.logical_level0_px.width;
 201       height = mt->surf.logical_level0_px.height;
 202    }
 203
 204    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 205                       brw_depth_writes_enabled(brw),
 206                       stencil_mt, brw->stencil_write_enabled,
 207                       hiz, width, height, depth, lod, min_array_element);
 208 }
 209
 210 /**
 211  * Should we set the PMA FIX ENABLE bit?
 212  *
 213  * To avoid unnecessary depth related stalls, we need to set this bit.
 214  * However, there is a very complicated formula which governs when it
 215  * is legal to do so.  This function computes that.
 216  *
 217  * See the documenation for the CACHE_MODE_1 register, bit 11.
 218  */
 219 static bool
 220 pma_fix_enable(const struct brw_context *brw)
 221 {
 222    const struct gl_context *ctx = &brw->ctx;
 223    /* BRW_NEW_FS_PROG_DATA */
 224    const struct brw_wm_prog_data *wm_prog_data =
 225       brw_wm_prog_data(brw->wm.base.prog_data);
 226    /* _NEW_BUFFERS */
 227    struct intel_renderbuffer *depth_irb =
 228       intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 229
 230    /* 3DSTATE_WM::ForceThreadDispatch is never used. */
 231    const bool wm_force_thread_dispatch = false;
 232
 233    /* 3DSTATE_RASTER::ForceSampleCount is never used. */
 234    const bool raster_force_sample_count_nonzero = false;
 235
 236    /* _NEW_BUFFERS:
 237     * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 238     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 239     */
 240    const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
 241
 242    /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
 243    const bool edsc_not_preps = !wm_prog_data->early_fragment_tests;
 244
 245    /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
 246    const bool pixel_shader_valid = true;
 247
 248    /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 249     *   3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 250     *   3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 251     *   3DSTATE_WM_HZ_OP::StencilBufferClear)
 252     *
 253     * HiZ operations are done outside of the normal state upload, so they're
 254     * definitely not happening now.
 255     */
 256    const bool in_hiz_op = false;
 257
 258    /* _NEW_DEPTH:
 259     * DEPTH_STENCIL_STATE::DepthTestEnable
 260     */
 261    const bool depth_test_enabled = depth_irb && ctx->Depth.Test;
 262
 263    /* _NEW_DEPTH:
 264     * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 265     * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
 266     */
 267    const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
 268
 269    /* _NEW_STENCIL:
 270     * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
 271     * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
 272     * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
 273     */
 274    const bool stencil_writes_enabled = brw->stencil_write_enabled;
 275
 276    /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
 277    const bool ps_computes_depth =
 278       wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
 279
 280    /* BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::PixelShaderKillsPixels
 281     * BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::oMask Present to RenderTarget
 282     * _NEW_MULTISAMPLE:         3DSTATE_PS_BLEND::AlphaToCoverageEnable
 283     * _NEW_COLOR:               3DSTATE_PS_BLEND::AlphaTestEnable
 284     * _NEW_BUFFERS:             3DSTATE_PS_BLEND::AlphaTestEnable
 285     *                           3DSTATE_PS_BLEND::AlphaToCoverageEnable
 286     *
 287     * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
 288     * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
 289     */
 290    const bool kill_pixel =
 291       wm_prog_data->uses_kill ||
 292       wm_prog_data->uses_omask ||
 293       _mesa_is_alpha_test_enabled(ctx) ||
 294       _mesa_is_alpha_to_coverage_enabled(ctx);
 295
 296    /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
 297    return !wm_force_thread_dispatch &&
 298           !raster_force_sample_count_nonzero &&
 299           hiz_enabled &&
 300           edsc_not_preps &&
 301           pixel_shader_valid &&
 302           !in_hiz_op &&
 303           depth_test_enabled &&
 304           (ps_computes_depth ||
 305            (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
 306 }
 307
 308 void
 309 gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 310 {
 311    /* If we haven't actually changed the value, bail now to avoid unnecessary
 312     * pipeline stalls and register writes.
 313     */
 314    if (brw->pma_stall_bits == pma_stall_bits)
 315       return;
 316
 317    brw->pma_stall_bits = pma_stall_bits;
 318
 319    /* According to the PIPE_CONTROL documentation, software should emit a
 320     * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
 321     * to the LRI.  If stencil buffer writes are enabled, then a Render Cache
 322     * Flush is also necessary.
 323     */
 324    const uint32_t render_cache_flush =
 325       brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
 326    brw_emit_pipe_control_flush(brw,
 327                                PIPE_CONTROL_CS_STALL |
 328                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 329                                render_cache_flush);
 330
 331    /* CACHE_MODE_1 is a non-privileged register. */
 332    BEGIN_BATCH(3);
 333    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 334    OUT_BATCH(GEN7_CACHE_MODE_1);
 335    OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
 336    ADVANCE_BATCH();
 337
 338    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 339     * Flush bits is often necessary.  We do it regardless because it's easier.
 340     * The render cache flush is also necessary if stencil writes are enabled.
 341     */
 342    brw_emit_pipe_control_flush(brw,
 343                                PIPE_CONTROL_DEPTH_STALL |
 344                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 345                                render_cache_flush);
 346
 347 }
 348
 349 static void
 350 gen8_emit_pma_stall_workaround(struct brw_context *brw)
 351 {
 352    uint32_t bits = 0;
 353
 354    if (brw->gen >= 9)
 355       return;
 356
 357    if (pma_fix_enable(brw))
 358       bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
 359
 360    gen8_write_pma_stall_bits(brw, bits);
 361 }
 362
 363 const struct brw_tracked_state gen8_pma_fix = {
 364    .dirty = {
 365       .mesa = _NEW_BUFFERS |
 366               _NEW_COLOR |
 367               _NEW_DEPTH |
 368               _NEW_MULTISAMPLE |
 369               _NEW_STENCIL,
 370       .brw = BRW_NEW_BLORP |
 371              BRW_NEW_FS_PROG_DATA,
 372    },
 373    .emit = gen8_emit_pma_stall_workaround
 374 };