src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "intel_resolve_map.h"
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31 #include "brw_defines.h"
  32
  33 /**
  34  * Helper function to emit depth related command packets.
  35  */
  36 static void
  37 emit_depth_packets(struct brw_context *brw,
  38                    struct intel_mipmap_tree *depth_mt,
  39                    uint32_t depthbuffer_format,
  40                    uint32_t depth_surface_type,
  41                    bool depth_writable,
  42                    struct intel_mipmap_tree *stencil_mt,
  43                    bool stencil_writable,
  44                    uint32_t stencil_offset,
  45                    bool hiz,
  46                    uint32_t width,
  47                    uint32_t height,
  48                    uint32_t depth,
  49                    uint32_t lod,
  50                    uint32_t min_array_element)
  51 {
  52    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
  53    if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
  54       assert(brw->hw_ctx);
  55       return;
  56    }
  57
  58    intel_emit_depth_stall_flushes(brw);
  59
  60    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  61    BEGIN_BATCH(8);
  62    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  63    OUT_BATCH(depth_surface_type << 29 |
  64              (depth_writable ? (1 << 28) : 0) |
  65              (stencil_mt != NULL && stencil_writable) << 27 |
  66              (hiz ? 1 : 0) << 22 |
  67              depthbuffer_format << 18 |
  68              (depth_mt ? depth_mt->region->pitch - 1 : 0));
  69    if (depth_mt) {
  70       OUT_RELOC64(depth_mt->region->bo,
  71                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  72    } else {
  73       OUT_BATCH(0);
  74       OUT_BATCH(0);
  75    }
  76    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  77    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | BDW_MOCS_WB);
  78    OUT_BATCH(0);
  79    OUT_BATCH(depth_mt ? depth_mt->qpitch >> 2 : 0);
  80    ADVANCE_BATCH();
  81
  82    if (!hiz) {
  83       BEGIN_BATCH(5);
  84       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  85       OUT_BATCH(0);
  86       OUT_BATCH(0);
  87       OUT_BATCH(0);
  88       OUT_BATCH(0);
  89       ADVANCE_BATCH();
  90    } else {
  91       BEGIN_BATCH(5);
  92       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  93       OUT_BATCH((depth_mt->hiz_mt->region->pitch - 1) | BDW_MOCS_WB << 25);
  94       OUT_RELOC64(depth_mt->hiz_mt->region->bo,
  95                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  96       OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2);
  97       ADVANCE_BATCH();
  98    }
  99
 100    if (stencil_mt == NULL) {
 101       BEGIN_BATCH(5);
 102       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 103       OUT_BATCH(0);
 104       OUT_BATCH(0);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       ADVANCE_BATCH();
 108    } else {
 109       BEGIN_BATCH(5);
 110       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 111       /* The stencil buffer has quirky pitch requirements.  From the Graphics
 112        * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
 113        * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
 114        * field "Surface Pitch":
 115        *
 116        *    The pitch must be set to 2x the value computed based on width, as
 117        *    the stencil buffer is stored with two rows interleaved.
 118        *
 119        * (Note that it is not 100% clear whether this intended to apply to
 120        * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
 121        * imply that it doesn't), however the comment appears on a "DevIVB+"
 122        * page (which would imply that it does).  Experiments with the hardware
 123        * indicate that it does.
 124        */
 125       OUT_BATCH(HSW_STENCIL_ENABLED | BDW_MOCS_WB << 22 |
 126                 (2 * stencil_mt->region->pitch - 1));
 127       OUT_RELOC64(stencil_mt->region->bo,
 128                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 129                   stencil_offset);
 130       OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
 131       ADVANCE_BATCH();
 132    }
 133
 134    BEGIN_BATCH(3);
 135    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 136    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 137    OUT_BATCH(1);
 138    ADVANCE_BATCH();
 139
 140    brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 141 }
 142
 143 /* Awful vtable-compatible function; should be cleaned up in the future. */
 144 void
 145 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 146                             struct intel_mipmap_tree *depth_mt,
 147                             uint32_t depth_offset,
 148                             uint32_t depthbuffer_format,
 149                             uint32_t depth_surface_type,
 150                             struct intel_mipmap_tree *stencil_mt,
 151                             bool hiz, bool separate_stencil,
 152                             uint32_t width, uint32_t height,
 153                             uint32_t tile_x, uint32_t tile_y)
 154 {
 155    struct gl_context *ctx = &brw->ctx;
 156    struct gl_framebuffer *fb = ctx->DrawBuffer;
 157    uint32_t surftype;
 158    unsigned int depth = 1;
 159    unsigned int min_array_element;
 160    GLenum gl_target = GL_TEXTURE_2D;
 161    unsigned int lod;
 162    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 163    const struct intel_renderbuffer *irb = NULL;
 164    const struct gl_renderbuffer *rb = NULL;
 165
 166    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 167    if (!irb)
 168       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 169    rb = (struct gl_renderbuffer *) irb;
 170
 171    if (rb) {
 172       depth = MAX2(rb->Depth, 1);
 173       if (rb->TexImage)
 174          gl_target = rb->TexImage->TexObject->Target;
 175    }
 176
 177    switch (gl_target) {
 178    case GL_TEXTURE_CUBE_MAP_ARRAY:
 179    case GL_TEXTURE_CUBE_MAP:
 180       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 181        * situation, but experiments show that gl_Layer doesn't work when we do
 182        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 183        * equivalent.
 184        */
 185       surftype = BRW_SURFACE_2D;
 186       depth *= 6;
 187       break;
 188    default:
 189       surftype = translate_tex_target(gl_target);
 190       break;
 191    }
 192
 193    if (fb->MaxNumLayers > 0 || !irb) {
 194       min_array_element = 0;
 195    } else if (irb->mt->num_samples > 1) {
 196       /* Convert physical to logical layer. */
 197       min_array_element = irb->mt_layer / irb->mt->num_samples;
 198    } else {
 199       min_array_element = irb->mt_layer;
 200    }
 201
 202    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 203
 204    if (mt) {
 205       width = mt->logical_width0;
 206       height = mt->logical_height0;
 207    }
 208
 209    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 210                       ctx->Depth.Mask != 0,
 211                       stencil_mt, ctx->Stencil._WriteEnabled,
 212                       brw->depthstencil.stencil_offset,
 213                       hiz, width, height, depth, lod, min_array_element);
 214 }
 215
 216 /**
 217  * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
 218  *
 219  * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
 220  * of the hardware documentation for details.
 221  */
 222 void
 223 gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 224               unsigned int level, unsigned int layer, enum gen6_hiz_op op)
 225 {
 226    if (op == GEN6_HIZ_OP_NONE)
 227       return;
 228
 229    assert(mt->first_level == 0);
 230    assert(mt->logical_depth0 >= 1);
 231
 232    /* The basic algorithm is:
 233     * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
 234     *   3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
 235     * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
 236     * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
 237     * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
 238     * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
 239     */
 240    emit_depth_packets(brw, mt,
 241                       brw_depth_format(brw, mt->format),
 242                       BRW_SURFACE_2D,
 243                       true, /* depth writes */
 244                       NULL, false, 0, /* no stencil for now */
 245                       true, /* hiz */
 246                       mt->logical_width0,
 247                       mt->logical_height0,
 248                       mt->logical_depth0,
 249                       level,
 250                       layer); /* min_array_element */
 251
 252    unsigned rect_width = minify(mt->logical_width0, level);
 253    unsigned rect_height = minify(mt->logical_height0, level);
 254
 255    BEGIN_BATCH(4);
 256    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 257    OUT_BATCH(0);
 258    OUT_BATCH(((rect_width - 1) & 0xffff) | ((rect_height - 1) << 16));
 259    OUT_BATCH(0);
 260    ADVANCE_BATCH();
 261
 262    /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
 263     * resolve or clear operation we want to perform.
 264     */
 265    uint32_t dw1 = 0;
 266
 267    switch (op) {
 268    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 269       dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE;
 270       break;
 271    case GEN6_HIZ_OP_HIZ_RESOLVE:
 272       dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
 273       break;
 274    case GEN6_HIZ_OP_DEPTH_CLEAR:
 275       dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
 276       break;
 277    case GEN6_HIZ_OP_NONE:
 278       assert(!"Should not get here.");
 279    }
 280
 281    if (mt->num_samples > 0)
 282       dw1 |= SET_FIELD(ffs(mt->num_samples) - 1, GEN8_WM_HZ_NUM_SAMPLES);
 283
 284    BEGIN_BATCH(5);
 285    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 286    OUT_BATCH(dw1);
 287    OUT_BATCH(0);
 288    OUT_BATCH(SET_FIELD(rect_width, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX) |
 289              SET_FIELD(rect_height, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX));
 290    OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK));
 291    ADVANCE_BATCH();
 292
 293    /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
 294     * Data", and no other bits set.  This causes 3DSTATE_WM_HZ_OP's state to
 295     * take effect, and spawns a rectangle primitive.
 296     */
 297    brw_emit_pipe_control_write(brw,
 298                                PIPE_CONTROL_WRITE_IMMEDIATE,
 299                                brw->batch.workaround_bo, 0, 0, 0);
 300
 301    /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
 302    BEGIN_BATCH(5);
 303    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 304    OUT_BATCH(0);
 305    OUT_BATCH(0);
 306    OUT_BATCH(0);
 307    OUT_BATCH(0);
 308    ADVANCE_BATCH();
 309
 310    /* Mark this buffer as needing a TC flush, as we've rendered to it. */
 311    brw_render_cache_set_add_bo(brw, mt->region->bo);
 312
 313    /* We've clobbered all of the depth packets, and the drawing rectangle,
 314     * so we need to ensure those packets are re-emitted before the next
 315     * primitive.
 316     *
 317     * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
 318     */
 319    brw->state.dirty.mesa |= _NEW_DEPTH | _NEW_BUFFERS;
 320 }