2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_fbo.h"
27 #include "brw_context.h"
28 #include "brw_state.h"
29 #include "brw_defines.h"
30 #include "compiler/brw_eu_defines.h"
32 #include "main/framebuffer.h"
35 * Helper function to emit depth related command packets.
38 emit_depth_packets(struct brw_context
*brw
,
39 struct intel_mipmap_tree
*depth_mt
,
40 uint32_t depthbuffer_format
,
41 uint32_t depth_surface_type
,
43 struct intel_mipmap_tree
*stencil_mt
,
44 bool stencil_writable
,
50 uint32_t min_array_element
)
52 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
54 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
55 if (!depth_mt
&& !stencil_mt
&& brw
->no_depth_or_stencil
) {
60 brw_emit_depth_stall_flushes(brw
);
62 /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
64 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (8 - 2));
65 OUT_BATCH(depth_surface_type
<< 29 |
66 (depth_writable
? (1 << 28) : 0) |
67 (stencil_mt
!= NULL
&& stencil_writable
) << 27 |
69 depthbuffer_format
<< 18 |
70 (depth_mt
? depth_mt
->pitch
- 1 : 0));
72 OUT_RELOC64(depth_mt
->bo
,
73 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
78 OUT_BATCH(((width
- 1) << 4) | ((height
- 1) << 18) | lod
);
79 OUT_BATCH(((depth
- 1) << 21) | (min_array_element
<< 10) | mocs_wb
);
81 OUT_BATCH(((depth
- 1) << 21) | (depth_mt
? depth_mt
->qpitch
>> 2 : 0));
86 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
95 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
96 OUT_BATCH((depth_mt
->hiz_buf
->pitch
- 1) | mocs_wb
<< 25);
97 OUT_RELOC64(depth_mt
->hiz_buf
->bo
,
98 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
99 OUT_BATCH(depth_mt
->hiz_buf
->qpitch
>> 2);
103 if (stencil_mt
== NULL
) {
105 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
113 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
114 OUT_BATCH(HSW_STENCIL_ENABLED
| mocs_wb
<< 22 |
115 (stencil_mt
->pitch
- 1));
116 OUT_RELOC64(stencil_mt
->bo
,
117 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
118 OUT_BATCH(stencil_mt
? stencil_mt
->qpitch
>> 2 : 0);
123 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
124 OUT_BATCH(depth_mt
? depth_mt
->fast_clear_color
.u32
[0] : 0);
128 brw
->no_depth_or_stencil
= !depth_mt
&& !stencil_mt
;
131 /* Awful vtable-compatible function; should be cleaned up in the future. */
133 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*depth_mt
,
135 uint32_t depth_offset
,
136 uint32_t depthbuffer_format
,
137 uint32_t depth_surface_type
,
138 struct intel_mipmap_tree
*stencil_mt
,
139 bool hiz
, bool separate_stencil
,
140 uint32_t width
, uint32_t height
,
141 uint32_t tile_x
, uint32_t tile_y
)
143 struct gl_context
*ctx
= &brw
->ctx
;
144 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
146 unsigned int depth
= 1;
147 unsigned int min_array_element
;
148 GLenum gl_target
= GL_TEXTURE_2D
;
150 const struct intel_mipmap_tree
*mt
= depth_mt
? depth_mt
: stencil_mt
;
151 const struct intel_renderbuffer
*irb
= NULL
;
152 const struct gl_renderbuffer
*rb
= NULL
;
154 irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
156 irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
157 rb
= (struct gl_renderbuffer
*) irb
;
160 depth
= MAX2(irb
->layer_count
, 1);
162 gl_target
= rb
->TexImage
->TexObject
->Target
;
166 case GL_TEXTURE_CUBE_MAP_ARRAY
:
167 case GL_TEXTURE_CUBE_MAP
:
168 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
169 * situation, but experiments show that gl_Layer doesn't work when we do
170 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
173 surftype
= BRW_SURFACE_2D
;
178 depth
= MAX2(mt
->logical_depth0
, 1);
179 surftype
= translate_tex_target(gl_target
);
181 case GL_TEXTURE_1D_ARRAY
:
184 /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
185 * textures but it does allow pretending it's a 2D texture
188 surftype
= BRW_SURFACE_2D
;
193 surftype
= translate_tex_target(gl_target
);
197 min_array_element
= irb
? irb
->mt_layer
: 0;
199 lod
= irb
? irb
->mt_level
- irb
->mt
->first_level
: 0;
202 width
= mt
->logical_width0
;
203 height
= mt
->logical_height0
;
206 emit_depth_packets(brw
, depth_mt
, brw_depthbuffer_format(brw
), surftype
,
207 brw_depth_writes_enabled(brw
),
208 stencil_mt
, brw
->stencil_write_enabled
,
209 hiz
, width
, height
, depth
, lod
, min_array_element
);
213 * Should we set the PMA FIX ENABLE bit?
215 * To avoid unnecessary depth related stalls, we need to set this bit.
216 * However, there is a very complicated formula which governs when it
217 * is legal to do so. This function computes that.
219 * See the documenation for the CACHE_MODE_1 register, bit 11.
222 pma_fix_enable(const struct brw_context
*brw
)
224 const struct gl_context
*ctx
= &brw
->ctx
;
225 /* BRW_NEW_FS_PROG_DATA */
226 const struct brw_wm_prog_data
*wm_prog_data
=
227 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
229 struct intel_renderbuffer
*depth_irb
=
230 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
232 /* 3DSTATE_WM::ForceThreadDispatch is never used. */
233 const bool wm_force_thread_dispatch
= false;
235 /* 3DSTATE_RASTER::ForceSampleCount is never used. */
236 const bool raster_force_sample_count_nonzero
= false;
239 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
240 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
242 const bool hiz_enabled
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
244 /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
245 const bool edsc_not_preps
= !wm_prog_data
->early_fragment_tests
;
247 /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
248 const bool pixel_shader_valid
= true;
250 /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
251 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
252 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
253 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
255 * HiZ operations are done outside of the normal state upload, so they're
256 * definitely not happening now.
258 const bool in_hiz_op
= false;
261 * DEPTH_STENCIL_STATE::DepthTestEnable
263 const bool depth_test_enabled
= depth_irb
&& ctx
->Depth
.Test
;
266 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
267 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
269 const bool depth_writes_enabled
= brw_depth_writes_enabled(brw
);
272 * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
273 * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
274 * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
276 const bool stencil_writes_enabled
= brw
->stencil_write_enabled
;
278 /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
279 const bool ps_computes_depth
=
280 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
282 /* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
283 * BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
284 * _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
285 * _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
286 * _NEW_BUFFERS: 3DSTATE_PS_BLEND::AlphaTestEnable
287 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable
289 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
290 * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
292 const bool kill_pixel
=
293 wm_prog_data
->uses_kill
||
294 wm_prog_data
->uses_omask
||
295 _mesa_is_alpha_test_enabled(ctx
) ||
296 _mesa_is_alpha_to_coverage_enabled(ctx
);
298 /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
299 return !wm_force_thread_dispatch
&&
300 !raster_force_sample_count_nonzero
&&
303 pixel_shader_valid
&&
305 depth_test_enabled
&&
306 (ps_computes_depth
||
307 (kill_pixel
&& (depth_writes_enabled
|| stencil_writes_enabled
)));
311 gen8_write_pma_stall_bits(struct brw_context
*brw
, uint32_t pma_stall_bits
)
313 /* If we haven't actually changed the value, bail now to avoid unnecessary
314 * pipeline stalls and register writes.
316 if (brw
->pma_stall_bits
== pma_stall_bits
)
319 brw
->pma_stall_bits
= pma_stall_bits
;
321 /* According to the PIPE_CONTROL documentation, software should emit a
322 * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
323 * to the LRI. If stencil buffer writes are enabled, then a Render Cache
324 * Flush is also necessary.
326 const uint32_t render_cache_flush
=
327 brw
->stencil_write_enabled
? PIPE_CONTROL_RENDER_TARGET_FLUSH
: 0;
328 brw_emit_pipe_control_flush(brw
,
329 PIPE_CONTROL_CS_STALL
|
330 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
333 /* CACHE_MODE_1 is a non-privileged register. */
335 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
336 OUT_BATCH(GEN7_CACHE_MODE_1
);
337 OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS
| pma_stall_bits
);
340 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
341 * Flush bits is often necessary. We do it regardless because it's easier.
342 * The render cache flush is also necessary if stencil writes are enabled.
344 brw_emit_pipe_control_flush(brw
,
345 PIPE_CONTROL_DEPTH_STALL
|
346 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
352 gen8_emit_pma_stall_workaround(struct brw_context
*brw
)
359 if (pma_fix_enable(brw
))
360 bits
|= GEN8_HIZ_NP_PMA_FIX_ENABLE
| GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE
;
362 gen8_write_pma_stall_bits(brw
, bits
);
365 const struct brw_tracked_state gen8_pma_fix
= {
367 .mesa
= _NEW_BUFFERS
|
372 .brw
= BRW_NEW_BLORP
|
373 BRW_NEW_FS_PROG_DATA
,
375 .emit
= gen8_emit_pma_stall_workaround