2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_fbo.h"
27 #include "intel_resolve_map.h"
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
33 * Helper function to emit depth related command packets.
36 emit_depth_packets(struct brw_context
*brw
,
37 struct intel_mipmap_tree
*depth_mt
,
38 uint32_t depthbuffer_format
,
39 uint32_t depth_surface_type
,
41 struct intel_mipmap_tree
*stencil_mt
,
42 bool stencil_writable
,
43 uint32_t stencil_offset
,
49 uint32_t min_array_element
)
51 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
52 if (!depth_mt
&& !stencil_mt
&& brw
->no_depth_or_stencil
) {
57 intel_emit_depth_stall_flushes(brw
);
59 /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
61 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (8 - 2));
62 OUT_BATCH(depth_surface_type
<< 29 |
63 (depth_writable
? (1 << 28) : 0) |
64 (stencil_mt
!= NULL
&& stencil_writable
) << 27 |
66 depthbuffer_format
<< 18 |
67 (depth_mt
? depth_mt
->pitch
- 1 : 0));
69 OUT_RELOC64(depth_mt
->bo
,
70 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
75 OUT_BATCH(((width
- 1) << 4) | ((height
- 1) << 18) | lod
);
76 OUT_BATCH(((depth
- 1) << 21) | (min_array_element
<< 10) | BDW_MOCS_WB
);
78 OUT_BATCH(((depth
- 1) << 21) | (depth_mt
? depth_mt
->qpitch
>> 2 : 0));
83 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
91 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
92 OUT_BATCH((depth_mt
->hiz_mt
->pitch
- 1) | BDW_MOCS_WB
<< 25);
93 OUT_RELOC64(depth_mt
->hiz_mt
->bo
,
94 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
95 OUT_BATCH(depth_mt
->hiz_mt
->qpitch
>> 2);
99 if (stencil_mt
== NULL
) {
101 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
109 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
110 /* The stencil buffer has quirky pitch requirements. From the Graphics
111 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
112 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
113 * field "Surface Pitch":
115 * The pitch must be set to 2x the value computed based on width, as
116 * the stencil buffer is stored with two rows interleaved.
118 * (Note that it is not 100% clear whether this intended to apply to
119 * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
120 * imply that it doesn't), however the comment appears on a "DevIVB+"
121 * page (which would imply that it does). Experiments with the hardware
122 * indicate that it does.
124 OUT_BATCH(HSW_STENCIL_ENABLED
| BDW_MOCS_WB
<< 22 |
125 (2 * stencil_mt
->pitch
- 1));
126 OUT_RELOC64(stencil_mt
->bo
,
127 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
129 OUT_BATCH(stencil_mt
? stencil_mt
->qpitch
>> 2 : 0);
134 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
135 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
139 brw
->no_depth_or_stencil
= !depth_mt
&& !stencil_mt
;
142 /* Awful vtable-compatible function; should be cleaned up in the future. */
144 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
145 struct intel_mipmap_tree
*depth_mt
,
146 uint32_t depth_offset
,
147 uint32_t depthbuffer_format
,
148 uint32_t depth_surface_type
,
149 struct intel_mipmap_tree
*stencil_mt
,
150 bool hiz
, bool separate_stencil
,
151 uint32_t width
, uint32_t height
,
152 uint32_t tile_x
, uint32_t tile_y
)
154 struct gl_context
*ctx
= &brw
->ctx
;
155 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
157 unsigned int depth
= 1;
158 unsigned int min_array_element
;
159 GLenum gl_target
= GL_TEXTURE_2D
;
161 const struct intel_mipmap_tree
*mt
= depth_mt
? depth_mt
: stencil_mt
;
162 const struct intel_renderbuffer
*irb
= NULL
;
163 const struct gl_renderbuffer
*rb
= NULL
;
165 irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
167 irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
168 rb
= (struct gl_renderbuffer
*) irb
;
171 depth
= MAX2(irb
->layer_count
, 1);
173 gl_target
= rb
->TexImage
->TexObject
->Target
;
177 case GL_TEXTURE_CUBE_MAP_ARRAY
:
178 case GL_TEXTURE_CUBE_MAP
:
179 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
180 * situation, but experiments show that gl_Layer doesn't work when we do
181 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
184 surftype
= BRW_SURFACE_2D
;
189 depth
= MAX2(mt
->logical_depth0
, 1);
192 surftype
= translate_tex_target(gl_target
);
196 min_array_element
= irb
? irb
->mt_layer
: 0;
198 lod
= irb
? irb
->mt_level
- irb
->mt
->first_level
: 0;
201 width
= mt
->logical_width0
;
202 height
= mt
->logical_height0
;
205 emit_depth_packets(brw
, depth_mt
, brw_depthbuffer_format(brw
), surftype
,
206 ctx
->Depth
.Mask
!= 0,
207 stencil_mt
, ctx
->Stencil
._WriteEnabled
,
208 brw
->depthstencil
.stencil_offset
,
209 hiz
, width
, height
, depth
, lod
, min_array_element
);
213 * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
215 * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
216 * of the hardware documentation for details.
219 gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
220 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
)
222 if (op
== GEN6_HIZ_OP_NONE
)
225 assert(mt
->first_level
== 0);
226 assert(mt
->logical_depth0
>= 1);
228 /* If we're operating on LOD 0, align to 8x4 to meet the alignment
229 * requirements for most HiZ operations. Otherwise, use the actual size
230 * to allow the hardware to calculate the miplevel offsets correctly.
232 uint32_t surface_width
= ALIGN(mt
->logical_width0
, level
== 0 ? 8 : 1);
233 uint32_t surface_height
= ALIGN(mt
->logical_height0
, level
== 0 ? 4 : 1);
235 /* The basic algorithm is:
236 * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
237 * 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
238 * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
239 * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
240 * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
241 * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
243 emit_depth_packets(brw
, mt
,
244 brw_depth_format(brw
, mt
->format
),
246 true, /* depth writes */
247 NULL
, false, 0, /* no stencil for now */
253 layer
); /* min_array_element */
255 /* Depth buffer clears and HiZ resolves must use an 8x4 aligned rectangle.
256 * Note that intel_miptree_level_enable_hiz disables HiZ for miplevels > 0
257 * which aren't 8x4 aligned, so expanding the size is safe - it'll just
258 * draw into empty padding space.
260 unsigned rect_width
= ALIGN(minify(mt
->logical_width0
, level
), 8);
261 unsigned rect_height
= ALIGN(minify(mt
->logical_height0
, level
), 4);
264 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
266 OUT_BATCH(((rect_width
- 1) & 0xffff) | ((rect_height
- 1) << 16));
270 /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
271 * resolve or clear operation we want to perform.
276 case GEN6_HIZ_OP_DEPTH_RESOLVE
:
277 dw1
|= GEN8_WM_HZ_DEPTH_RESOLVE
;
279 case GEN6_HIZ_OP_HIZ_RESOLVE
:
280 dw1
|= GEN8_WM_HZ_HIZ_RESOLVE
;
282 case GEN6_HIZ_OP_DEPTH_CLEAR
:
283 dw1
|= GEN8_WM_HZ_DEPTH_CLEAR
;
285 case GEN6_HIZ_OP_NONE
:
286 unreachable("Should not get here.");
289 if (mt
->num_samples
> 0)
290 dw1
|= SET_FIELD(ffs(mt
->num_samples
) - 1, GEN8_WM_HZ_NUM_SAMPLES
);
293 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
296 OUT_BATCH(SET_FIELD(rect_width
, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX
) |
297 SET_FIELD(rect_height
, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX
));
298 OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK
));
301 /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
302 * Data", and no other bits set. This causes 3DSTATE_WM_HZ_OP's state to
303 * take effect, and spawns a rectangle primitive.
305 brw_emit_pipe_control_write(brw
,
306 PIPE_CONTROL_WRITE_IMMEDIATE
,
307 brw
->batch
.workaround_bo
, 0, 0, 0);
309 /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
311 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
318 /* Mark this buffer as needing a TC flush, as we've rendered to it. */
319 brw_render_cache_set_add_bo(brw
, mt
->bo
);
321 /* We've clobbered all of the depth packets, and the drawing rectangle,
322 * so we need to ensure those packets are re-emitted before the next
325 * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
327 SET_DIRTY_BIT(mesa
, _NEW_DEPTH
| _NEW_BUFFERS
);