2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_batchbuffer.h"
25 #include "intel_mipmap_tree.h"
26 #include "intel_fbo.h"
27 #include "intel_resolve_map.h"
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "main/framebuffer.h"
36 * Helper function to emit depth related command packets.
39 emit_depth_packets(struct brw_context
*brw
,
40 struct intel_mipmap_tree
*depth_mt
,
41 uint32_t depthbuffer_format
,
42 uint32_t depth_surface_type
,
44 struct intel_mipmap_tree
*stencil_mt
,
45 bool stencil_writable
,
51 uint32_t min_array_element
)
53 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
55 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
56 if (!depth_mt
&& !stencil_mt
&& brw
->no_depth_or_stencil
) {
61 brw_emit_depth_stall_flushes(brw
);
63 /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
65 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER
<< 16 | (8 - 2));
66 OUT_BATCH(depth_surface_type
<< 29 |
67 (depth_writable
? (1 << 28) : 0) |
68 (stencil_mt
!= NULL
&& stencil_writable
) << 27 |
70 depthbuffer_format
<< 18 |
71 (depth_mt
? depth_mt
->pitch
- 1 : 0));
73 OUT_RELOC64(depth_mt
->bo
,
74 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
79 OUT_BATCH(((width
- 1) << 4) | ((height
- 1) << 18) | lod
);
80 OUT_BATCH(((depth
- 1) << 21) | (min_array_element
<< 10) | mocs_wb
);
82 OUT_BATCH(((depth
- 1) << 21) | (depth_mt
? depth_mt
->qpitch
>> 2 : 0));
87 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
96 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER
<< 16 | (5 - 2));
97 OUT_BATCH((depth_mt
->hiz_buf
->aux_base
.pitch
- 1) | mocs_wb
<< 25);
98 OUT_RELOC64(depth_mt
->hiz_buf
->aux_base
.bo
,
99 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
100 OUT_BATCH(depth_mt
->hiz_buf
->aux_base
.qpitch
>> 2);
104 if (stencil_mt
== NULL
) {
106 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
114 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
<< 16 | (5 - 2));
115 /* The stencil buffer has quirky pitch requirements. From the Graphics
116 * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
117 * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
118 * field "Surface Pitch":
120 * The pitch must be set to 2x the value computed based on width, as
121 * the stencil buffer is stored with two rows interleaved.
123 * (Note that it is not 100% clear whether this intended to apply to
124 * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
125 * imply that it doesn't), however the comment appears on a "DevIVB+"
126 * page (which would imply that it does). Experiments with the hardware
127 * indicate that it does.
129 OUT_BATCH(HSW_STENCIL_ENABLED
| mocs_wb
<< 22 |
130 (2 * stencil_mt
->pitch
- 1));
131 OUT_RELOC64(stencil_mt
->bo
,
132 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
133 OUT_BATCH(stencil_mt
? stencil_mt
->qpitch
>> 2 : 0);
138 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS
<< 16 | (3 - 2));
139 OUT_BATCH(depth_mt
? depth_mt
->fast_clear_color
.u32
[0] : 0);
143 brw
->no_depth_or_stencil
= !depth_mt
&& !stencil_mt
;
146 /* Awful vtable-compatible function; should be cleaned up in the future. */
148 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
149 struct intel_mipmap_tree
*depth_mt
,
150 uint32_t depth_offset
,
151 uint32_t depthbuffer_format
,
152 uint32_t depth_surface_type
,
153 struct intel_mipmap_tree
*stencil_mt
,
154 bool hiz
, bool separate_stencil
,
155 uint32_t width
, uint32_t height
,
156 uint32_t tile_x
, uint32_t tile_y
)
158 struct gl_context
*ctx
= &brw
->ctx
;
159 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
161 unsigned int depth
= 1;
162 unsigned int min_array_element
;
163 GLenum gl_target
= GL_TEXTURE_2D
;
165 const struct intel_mipmap_tree
*mt
= depth_mt
? depth_mt
: stencil_mt
;
166 const struct intel_renderbuffer
*irb
= NULL
;
167 const struct gl_renderbuffer
*rb
= NULL
;
169 irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
171 irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
172 rb
= (struct gl_renderbuffer
*) irb
;
175 depth
= MAX2(irb
->layer_count
, 1);
177 gl_target
= rb
->TexImage
->TexObject
->Target
;
181 case GL_TEXTURE_CUBE_MAP_ARRAY
:
182 case GL_TEXTURE_CUBE_MAP
:
183 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
184 * situation, but experiments show that gl_Layer doesn't work when we do
185 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
188 surftype
= BRW_SURFACE_2D
;
193 depth
= MAX2(mt
->logical_depth0
, 1);
194 surftype
= translate_tex_target(gl_target
);
196 case GL_TEXTURE_1D_ARRAY
:
199 /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
200 * textures but it does allow pretending it's a 2D texture
203 surftype
= BRW_SURFACE_2D
;
208 surftype
= translate_tex_target(gl_target
);
212 min_array_element
= irb
? irb
->mt_layer
: 0;
214 lod
= irb
? irb
->mt_level
- irb
->mt
->first_level
: 0;
217 width
= mt
->logical_width0
;
218 height
= mt
->logical_height0
;
221 emit_depth_packets(brw
, depth_mt
, brw_depthbuffer_format(brw
), surftype
,
222 brw_depth_writes_enabled(brw
),
223 stencil_mt
, ctx
->Stencil
._WriteEnabled
,
224 hiz
, width
, height
, depth
, lod
, min_array_element
);
228 * Should we set the PMA FIX ENABLE bit?
230 * To avoid unnecessary depth related stalls, we need to set this bit.
231 * However, there is a very complicated formula which governs when it
232 * is legal to do so. This function computes that.
234 * See the documenation for the CACHE_MODE_1 register, bit 11.
237 pma_fix_enable(const struct brw_context
*brw
)
239 const struct gl_context
*ctx
= &brw
->ctx
;
240 /* BRW_NEW_FS_PROG_DATA */
241 const struct brw_wm_prog_data
*wm_prog_data
=
242 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
244 struct intel_renderbuffer
*depth_irb
=
245 intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
247 /* 3DSTATE_WM::ForceThreadDispatch is never used. */
248 const bool wm_force_thread_dispatch
= false;
250 /* 3DSTATE_RASTER::ForceSampleCount is never used. */
251 const bool raster_force_sample_count_nonzero
= false;
254 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
255 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
257 const bool hiz_enabled
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
259 /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
260 const bool edsc_not_preps
= !wm_prog_data
->early_fragment_tests
;
262 /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
263 const bool pixel_shader_valid
= true;
265 /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
266 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
267 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
268 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
270 * HiZ operations are done outside of the normal state upload, so they're
271 * definitely not happening now.
273 const bool in_hiz_op
= false;
276 * DEPTH_STENCIL_STATE::DepthTestEnable
278 const bool depth_test_enabled
= depth_irb
&& ctx
->Depth
.Test
;
281 * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
282 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
284 const bool depth_writes_enabled
= brw_depth_writes_enabled(brw
);
287 * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
288 * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
289 * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
291 const bool stencil_writes_enabled
= ctx
->Stencil
._WriteEnabled
;
293 /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
294 const bool ps_computes_depth
=
295 wm_prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
297 /* BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
298 * BRW_NEW_FS_PROG_DATA: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
299 * _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
300 * _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
301 * _NEW_BUFFERS: 3DSTATE_PS_BLEND::AlphaTestEnable
302 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable
304 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
305 * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
307 const bool kill_pixel
=
308 wm_prog_data
->uses_kill
||
309 wm_prog_data
->uses_omask
||
310 _mesa_is_alpha_test_enabled(ctx
) ||
311 _mesa_is_alpha_to_coverage_enabled(ctx
);
313 /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
314 return !wm_force_thread_dispatch
&&
315 !raster_force_sample_count_nonzero
&&
318 pixel_shader_valid
&&
320 depth_test_enabled
&&
321 (ps_computes_depth
||
322 (kill_pixel
&& (depth_writes_enabled
|| stencil_writes_enabled
)));
326 gen8_write_pma_stall_bits(struct brw_context
*brw
, uint32_t pma_stall_bits
)
328 struct gl_context
*ctx
= &brw
->ctx
;
330 /* If we haven't actually changed the value, bail now to avoid unnecessary
331 * pipeline stalls and register writes.
333 if (brw
->pma_stall_bits
== pma_stall_bits
)
336 brw
->pma_stall_bits
= pma_stall_bits
;
338 /* According to the PIPE_CONTROL documentation, software should emit a
339 * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
340 * to the LRI. If stencil buffer writes are enabled, then a Render Cache
341 * Flush is also necessary.
343 const uint32_t render_cache_flush
=
344 ctx
->Stencil
._WriteEnabled
? PIPE_CONTROL_RENDER_TARGET_FLUSH
: 0;
345 brw_emit_pipe_control_flush(brw
,
346 PIPE_CONTROL_CS_STALL
|
347 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
350 /* CACHE_MODE_1 is a non-privileged register. */
352 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
353 OUT_BATCH(GEN7_CACHE_MODE_1
);
354 OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS
| pma_stall_bits
);
357 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
358 * Flush bits is often necessary. We do it regardless because it's easier.
359 * The render cache flush is also necessary if stencil writes are enabled.
361 brw_emit_pipe_control_flush(brw
,
362 PIPE_CONTROL_DEPTH_STALL
|
363 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
369 gen8_emit_pma_stall_workaround(struct brw_context
*brw
)
376 if (pma_fix_enable(brw
))
377 bits
|= GEN8_HIZ_NP_PMA_FIX_ENABLE
| GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE
;
379 gen8_write_pma_stall_bits(brw
, bits
);
382 const struct brw_tracked_state gen8_pma_fix
= {
384 .mesa
= _NEW_BUFFERS
|
389 .brw
= BRW_NEW_BLORP
|
390 BRW_NEW_FS_PROG_DATA
,
392 .emit
= gen8_emit_pma_stall_workaround
396 * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
398 * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
399 * of the hardware documentation for details.
402 gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
403 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
)
405 if (op
== BLORP_HIZ_OP_NONE
)
408 /* Disable the PMA stall fix since we're about to do a HiZ operation. */
410 gen8_write_pma_stall_bits(brw
, 0);
412 assert(mt
->first_level
== 0);
413 assert(mt
->logical_depth0
>= 1);
415 /* If we're operating on LOD 0, align to 8x4 to meet the alignment
416 * requirements for most HiZ operations. Otherwise, use the actual size
417 * to allow the hardware to calculate the miplevel offsets correctly.
419 uint32_t surface_width
= ALIGN(mt
->logical_width0
, level
== 0 ? 8 : 1);
420 uint32_t surface_height
= ALIGN(mt
->logical_height0
, level
== 0 ? 4 : 1);
422 /* From the documentation for 3DSTATE_WM_HZ_OP: "3DSTATE_MULTISAMPLE packet
423 * must be used prior to this packet to change the Number of Multisamples.
424 * This packet must not be used to change Number of Multisamples in a
425 * rendering sequence."
427 if (brw
->num_samples
!= mt
->num_samples
) {
428 gen8_emit_3dstate_multisample(brw
, mt
->num_samples
);
429 brw
->NewGLState
|= _NEW_MULTISAMPLE
;
432 /* The basic algorithm is:
433 * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
434 * 3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
435 * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
436 * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
437 * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
438 * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
440 emit_depth_packets(brw
, mt
,
441 brw_depth_format(brw
, mt
->format
),
443 true, /* depth writes */
444 NULL
, false, /* no stencil for now */
450 layer
); /* min_array_element */
452 /* Depth buffer clears and HiZ resolves must use an 8x4 aligned rectangle.
453 * Note that intel_miptree_level_enable_hiz disables HiZ for miplevels > 0
454 * which aren't 8x4 aligned, so expanding the size is safe - it'll just
455 * draw into empty padding space.
457 unsigned rect_width
= ALIGN(minify(mt
->logical_width0
, level
), 8);
458 unsigned rect_height
= ALIGN(minify(mt
->logical_height0
, level
), 4);
461 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
463 OUT_BATCH(((rect_width
- 1) & 0xffff) | ((rect_height
- 1) << 16));
467 /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
468 * resolve or clear operation we want to perform.
473 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
474 dw1
|= GEN8_WM_HZ_DEPTH_RESOLVE
;
476 case BLORP_HIZ_OP_HIZ_RESOLVE
:
477 dw1
|= GEN8_WM_HZ_HIZ_RESOLVE
;
479 case BLORP_HIZ_OP_DEPTH_CLEAR
:
480 dw1
|= GEN8_WM_HZ_DEPTH_CLEAR
;
482 /* The "Clear Rectangle X Max" (and Y Max) fields are exclusive,
483 * rather than inclusive, and limited to 16383. This means that
484 * for a 16384x16384 render target, we would miss the last row
485 * or column of pixels along the edge.
487 * To work around this, we have to set the "Full Surface Depth
488 * and Stencil Clear" bit. We can do this in all cases because
489 * we always clear the full rectangle anyway. We'll need to
490 * change this if we ever add scissored clear support.
492 dw1
|= GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR
;
494 case BLORP_HIZ_OP_NONE
:
495 unreachable("Should not get here.");
498 if (mt
->num_samples
> 0)
499 dw1
|= SET_FIELD(ffs(mt
->num_samples
) - 1, GEN8_WM_HZ_NUM_SAMPLES
);
502 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
505 OUT_BATCH(SET_FIELD(rect_width
, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX
) |
506 SET_FIELD(rect_height
, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX
));
507 OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK
));
510 /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
511 * Data", and no other bits set. This causes 3DSTATE_WM_HZ_OP's state to
512 * take effect, and spawns a rectangle primitive.
514 brw_emit_pipe_control_write(brw
,
515 PIPE_CONTROL_WRITE_IMMEDIATE
,
516 brw
->workaround_bo
, 0, 0, 0);
518 /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
520 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
527 /* Mark this buffer as needing a TC flush, as we've rendered to it. */
528 brw_render_cache_set_add_bo(brw
, mt
->bo
);
530 /* We've clobbered all of the depth packets, and the drawing rectangle,
531 * so we need to ensure those packets are re-emitted before the next
534 * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
536 brw
->NewGLState
|= _NEW_DEPTH
| _NEW_BUFFERS
;