src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_fbo.h"
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30 #include "compiler/brw_eu_defines.h"
  31 #include "brw_wm.h"
  32 #include "main/framebuffer.h"
  33
  34 /**
  35  * Helper function to emit depth related command packets.
  36  */
  37 static void
  38 emit_depth_packets(struct brw_context *brw,
  39                    struct intel_mipmap_tree *depth_mt,
  40                    uint32_t depthbuffer_format,
  41                    uint32_t depth_surface_type,
  42                    bool depth_writable,
  43                    struct intel_mipmap_tree *stencil_mt,
  44                    bool stencil_writable,
  45                    bool hiz,
  46                    uint32_t width,
  47                    uint32_t height,
  48                    uint32_t depth,
  49                    uint32_t lod,
  50                    uint32_t min_array_element)
  51 {
  52    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  53
  54    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
  55    if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
  56       assert(brw->hw_ctx);
  57       return;
  58    }
  59
  60    brw_emit_depth_stall_flushes(brw);
  61
  62    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  63    BEGIN_BATCH(8);
  64    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  65    OUT_BATCH(depth_surface_type << 29 |
  66              (depth_writable ? (1 << 28) : 0) |
  67              (stencil_mt != NULL && stencil_writable) << 27 |
  68              (hiz ? 1 : 0) << 22 |
  69              depthbuffer_format << 18 |
  70              (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
  71    if (depth_mt) {
  72       OUT_RELOC64(depth_mt->bo,
  73                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  74    } else {
  75       OUT_BATCH(0);
  76       OUT_BATCH(0);
  77    }
  78    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  79    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
  80    OUT_BATCH(0);
  81    OUT_BATCH(((depth - 1) << 21) |
  82               (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
  83    ADVANCE_BATCH();
  84
  85    if (!hiz) {
  86       BEGIN_BATCH(5);
  87       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90       OUT_BATCH(0);
  91       OUT_BATCH(0);
  92       ADVANCE_BATCH();
  93    } else {
  94       assert(depth_mt);
  95       BEGIN_BATCH(5);
  96       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  97       OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
  98       OUT_RELOC64(depth_mt->hiz_buf->bo,
  99                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 100       OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
 101       ADVANCE_BATCH();
 102    }
 103
 104    if (stencil_mt == NULL) {
 105       BEGIN_BATCH(5);
 106       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       OUT_BATCH(0);
 111       ADVANCE_BATCH();
 112    } else {
 113       BEGIN_BATCH(5);
 114       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 115       OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
 116                 (stencil_mt->surf.row_pitch - 1));
 117       OUT_RELOC64(stencil_mt->bo,
 118                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 119       OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
 120       ADVANCE_BATCH();
 121    }
 122
 123    BEGIN_BATCH(3);
 124    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 125    OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);
 126    OUT_BATCH(1);
 127    ADVANCE_BATCH();
 128
 129    brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 130 }
 131
 132 /* Awful vtable-compatible function; should be cleaned up in the future. */
 133 void
 134 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 135                             struct intel_mipmap_tree *depth_mt,
 136                             uint32_t depth_offset,
 137                             uint32_t depthbuffer_format,
 138                             uint32_t depth_surface_type,
 139                             struct intel_mipmap_tree *stencil_mt,
 140                             bool hiz, bool separate_stencil,
 141                             uint32_t width, uint32_t height,
 142                             uint32_t tile_x, uint32_t tile_y)
 143 {
 144    struct gl_context *ctx = &brw->ctx;
 145    struct gl_framebuffer *fb = ctx->DrawBuffer;
 146    uint32_t surftype;
 147    unsigned int depth = 1;
 148    unsigned int min_array_element;
 149    GLenum gl_target = GL_TEXTURE_2D;
 150    unsigned int lod;
 151    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 152    const struct intel_renderbuffer *irb = NULL;
 153    const struct gl_renderbuffer *rb = NULL;
 154
 155    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 156    if (!irb)
 157       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 158    rb = (struct gl_renderbuffer *) irb;
 159
 160    if (rb) {
 161       depth = MAX2(irb->layer_count, 1);
 162       if (rb->TexImage)
 163          gl_target = rb->TexImage->TexObject->Target;
 164    }
 165
 166    switch (gl_target) {
 167    case GL_TEXTURE_CUBE_MAP_ARRAY:
 168    case GL_TEXTURE_CUBE_MAP:
 169       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 170        * situation, but experiments show that gl_Layer doesn't work when we do
 171        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 172        * equivalent.
 173        */
 174       surftype = BRW_SURFACE_2D;
 175       depth *= 6;
 176       break;
 177    case GL_TEXTURE_3D:
 178       assert(mt);
 179       depth = mt->surf.logical_level0_px.depth;
 180       surftype = translate_tex_target(gl_target);
 181       break;
 182    case GL_TEXTURE_1D_ARRAY:
 183    case GL_TEXTURE_1D:
 184       if (brw->gen >= 9) {
 185          /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
 186           * textures but it does allow pretending it's a 2D texture
 187           * instead.
 188           */
 189          surftype = BRW_SURFACE_2D;
 190          break;
 191       }
 192       /* fallthrough */
 193    default:
 194       surftype = translate_tex_target(gl_target);
 195       break;
 196    }
 197
 198    min_array_element = irb ? irb->mt_layer : 0;
 199
 200    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 201
 202    if (mt) {
 203       width = mt->surf.logical_level0_px.width;
 204       height = mt->surf.logical_level0_px.height;
 205    }
 206
 207    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 208                       brw_depth_writes_enabled(brw),
 209                       stencil_mt, brw->stencil_write_enabled,
 210                       hiz, width, height, depth, lod, min_array_element);
 211 }
 212
 213 /**
 214  * Should we set the PMA FIX ENABLE bit?
 215  *
 216  * To avoid unnecessary depth related stalls, we need to set this bit.
 217  * However, there is a very complicated formula which governs when it
 218  * is legal to do so.  This function computes that.
 219  *
 220  * See the documenation for the CACHE_MODE_1 register, bit 11.
 221  */
 222 static bool
 223 pma_fix_enable(const struct brw_context *brw)
 224 {
 225    const struct gl_context *ctx = &brw->ctx;
 226    /* BRW_NEW_FS_PROG_DATA */
 227    const struct brw_wm_prog_data *wm_prog_data =
 228       brw_wm_prog_data(brw->wm.base.prog_data);
 229    /* _NEW_BUFFERS */
 230    struct intel_renderbuffer *depth_irb =
 231       intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 232
 233    /* 3DSTATE_WM::ForceThreadDispatch is never used. */
 234    const bool wm_force_thread_dispatch = false;
 235
 236    /* 3DSTATE_RASTER::ForceSampleCount is never used. */
 237    const bool raster_force_sample_count_nonzero = false;
 238
 239    /* _NEW_BUFFERS:
 240     * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 241     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 242     */
 243    const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
 244
 245    /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
 246    const bool edsc_not_preps = !wm_prog_data->early_fragment_tests;
 247
 248    /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
 249    const bool pixel_shader_valid = true;
 250
 251    /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 252     *   3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 253     *   3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 254     *   3DSTATE_WM_HZ_OP::StencilBufferClear)
 255     *
 256     * HiZ operations are done outside of the normal state upload, so they're
 257     * definitely not happening now.
 258     */
 259    const bool in_hiz_op = false;
 260
 261    /* _NEW_DEPTH:
 262     * DEPTH_STENCIL_STATE::DepthTestEnable
 263     */
 264    const bool depth_test_enabled = depth_irb && ctx->Depth.Test;
 265
 266    /* _NEW_DEPTH:
 267     * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 268     * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
 269     */
 270    const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
 271
 272    /* _NEW_STENCIL:
 273     * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
 274     * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
 275     * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
 276     */
 277    const bool stencil_writes_enabled = brw->stencil_write_enabled;
 278
 279    /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
 280    const bool ps_computes_depth =
 281       wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
 282
 283    /* BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::PixelShaderKillsPixels
 284     * BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::oMask Present to RenderTarget
 285     * _NEW_MULTISAMPLE:         3DSTATE_PS_BLEND::AlphaToCoverageEnable
 286     * _NEW_COLOR:               3DSTATE_PS_BLEND::AlphaTestEnable
 287     * _NEW_BUFFERS:             3DSTATE_PS_BLEND::AlphaTestEnable
 288     *                           3DSTATE_PS_BLEND::AlphaToCoverageEnable
 289     *
 290     * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
 291     * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
 292     */
 293    const bool kill_pixel =
 294       wm_prog_data->uses_kill ||
 295       wm_prog_data->uses_omask ||
 296       _mesa_is_alpha_test_enabled(ctx) ||
 297       _mesa_is_alpha_to_coverage_enabled(ctx);
 298
 299    /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
 300    return !wm_force_thread_dispatch &&
 301           !raster_force_sample_count_nonzero &&
 302           hiz_enabled &&
 303           edsc_not_preps &&
 304           pixel_shader_valid &&
 305           !in_hiz_op &&
 306           depth_test_enabled &&
 307           (ps_computes_depth ||
 308            (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
 309 }
 310
 311 void
 312 gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 313 {
 314    /* If we haven't actually changed the value, bail now to avoid unnecessary
 315     * pipeline stalls and register writes.
 316     */
 317    if (brw->pma_stall_bits == pma_stall_bits)
 318       return;
 319
 320    brw->pma_stall_bits = pma_stall_bits;
 321
 322    /* According to the PIPE_CONTROL documentation, software should emit a
 323     * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
 324     * to the LRI.  If stencil buffer writes are enabled, then a Render Cache
 325     * Flush is also necessary.
 326     */
 327    const uint32_t render_cache_flush =
 328       brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
 329    brw_emit_pipe_control_flush(brw,
 330                                PIPE_CONTROL_CS_STALL |
 331                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 332                                render_cache_flush);
 333
 334    /* CACHE_MODE_1 is a non-privileged register. */
 335    BEGIN_BATCH(3);
 336    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 337    OUT_BATCH(GEN7_CACHE_MODE_1);
 338    OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
 339    ADVANCE_BATCH();
 340
 341    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 342     * Flush bits is often necessary.  We do it regardless because it's easier.
 343     * The render cache flush is also necessary if stencil writes are enabled.
 344     */
 345    brw_emit_pipe_control_flush(brw,
 346                                PIPE_CONTROL_DEPTH_STALL |
 347                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 348                                render_cache_flush);
 349
 350 }
 351
 352 static void
 353 gen8_emit_pma_stall_workaround(struct brw_context *brw)
 354 {
 355    uint32_t bits = 0;
 356
 357    if (brw->gen >= 9)
 358       return;
 359
 360    if (pma_fix_enable(brw))
 361       bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
 362
 363    gen8_write_pma_stall_bits(brw, bits);
 364 }
 365
 366 const struct brw_tracked_state gen8_pma_fix = {
 367    .dirty = {
 368       .mesa = _NEW_BUFFERS |
 369               _NEW_COLOR |
 370               _NEW_DEPTH |
 371               _NEW_MULTISAMPLE |
 372               _NEW_STENCIL,
 373       .brw = BRW_NEW_BLORP |
 374              BRW_NEW_FS_PROG_DATA,
 375    },
 376    .emit = gen8_emit_pma_stall_workaround
 377 };