src/mesa/drivers/dri/i965/gen8_depth_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_fbo.h"
  27 #include "intel_resolve_map.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_eu_defines.h"
  32 #include "brw_wm.h"
  33 #include "main/framebuffer.h"
  34
  35 /**
  36  * Helper function to emit depth related command packets.
  37  */
  38 static void
  39 emit_depth_packets(struct brw_context *brw,
  40                    struct intel_mipmap_tree *depth_mt,
  41                    uint32_t depthbuffer_format,
  42                    uint32_t depth_surface_type,
  43                    bool depth_writable,
  44                    struct intel_mipmap_tree *stencil_mt,
  45                    bool stencil_writable,
  46                    bool hiz,
  47                    uint32_t width,
  48                    uint32_t height,
  49                    uint32_t depth,
  50                    uint32_t lod,
  51                    uint32_t min_array_element)
  52 {
  53    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  54
  55    /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
  56    if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
  57       assert(brw->hw_ctx);
  58       return;
  59    }
  60
  61    brw_emit_depth_stall_flushes(brw);
  62
  63    /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
  64    BEGIN_BATCH(8);
  65    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
  66    OUT_BATCH(depth_surface_type << 29 |
  67              (depth_writable ? (1 << 28) : 0) |
  68              (stencil_mt != NULL && stencil_writable) << 27 |
  69              (hiz ? 1 : 0) << 22 |
  70              depthbuffer_format << 18 |
  71              (depth_mt ? depth_mt->pitch - 1 : 0));
  72    if (depth_mt) {
  73       OUT_RELOC64(depth_mt->bo,
  74                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  75    } else {
  76       OUT_BATCH(0);
  77       OUT_BATCH(0);
  78    }
  79    OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
  80    OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
  81    OUT_BATCH(0);
  82    OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0));
  83    ADVANCE_BATCH();
  84
  85    if (!hiz) {
  86       BEGIN_BATCH(5);
  87       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90       OUT_BATCH(0);
  91       OUT_BATCH(0);
  92       ADVANCE_BATCH();
  93    } else {
  94       assert(depth_mt);
  95       BEGIN_BATCH(5);
  96       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
  97       OUT_BATCH((depth_mt->hiz_buf->aux_base.pitch - 1) | mocs_wb << 25);
  98       OUT_RELOC64(depth_mt->hiz_buf->aux_base.bo,
  99                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 100       OUT_BATCH(depth_mt->hiz_buf->aux_base.qpitch >> 2);
 101       ADVANCE_BATCH();
 102    }
 103
 104    if (stencil_mt == NULL) {
 105       BEGIN_BATCH(5);
 106       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       OUT_BATCH(0);
 110       OUT_BATCH(0);
 111       ADVANCE_BATCH();
 112    } else {
 113       BEGIN_BATCH(5);
 114       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
 115       /* The stencil buffer has quirky pitch requirements.  From the Graphics
 116        * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
 117        * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
 118        * field "Surface Pitch":
 119        *
 120        *    The pitch must be set to 2x the value computed based on width, as
 121        *    the stencil buffer is stored with two rows interleaved.
 122        *
 123        * (Note that it is not 100% clear whether this intended to apply to
 124        * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
 125        * imply that it doesn't), however the comment appears on a "DevIVB+"
 126        * page (which would imply that it does).  Experiments with the hardware
 127        * indicate that it does.
 128        */
 129       OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
 130                 (2 * stencil_mt->pitch - 1));
 131       OUT_RELOC64(stencil_mt->bo,
 132                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 133       OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
 134       ADVANCE_BATCH();
 135    }
 136
 137    BEGIN_BATCH(3);
 138    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 139    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
 140    OUT_BATCH(1);
 141    ADVANCE_BATCH();
 142
 143    brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 144 }
 145
 146 /* Awful vtable-compatible function; should be cleaned up in the future. */
 147 void
 148 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 149                             struct intel_mipmap_tree *depth_mt,
 150                             uint32_t depth_offset,
 151                             uint32_t depthbuffer_format,
 152                             uint32_t depth_surface_type,
 153                             struct intel_mipmap_tree *stencil_mt,
 154                             bool hiz, bool separate_stencil,
 155                             uint32_t width, uint32_t height,
 156                             uint32_t tile_x, uint32_t tile_y)
 157 {
 158    struct gl_context *ctx = &brw->ctx;
 159    struct gl_framebuffer *fb = ctx->DrawBuffer;
 160    uint32_t surftype;
 161    unsigned int depth = 1;
 162    unsigned int min_array_element;
 163    GLenum gl_target = GL_TEXTURE_2D;
 164    unsigned int lod;
 165    const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
 166    const struct intel_renderbuffer *irb = NULL;
 167    const struct gl_renderbuffer *rb = NULL;
 168
 169    irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 170    if (!irb)
 171       irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 172    rb = (struct gl_renderbuffer *) irb;
 173
 174    if (rb) {
 175       depth = MAX2(irb->layer_count, 1);
 176       if (rb->TexImage)
 177          gl_target = rb->TexImage->TexObject->Target;
 178    }
 179
 180    switch (gl_target) {
 181    case GL_TEXTURE_CUBE_MAP_ARRAY:
 182    case GL_TEXTURE_CUBE_MAP:
 183       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 184        * situation, but experiments show that gl_Layer doesn't work when we do
 185        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 186        * equivalent.
 187        */
 188       surftype = BRW_SURFACE_2D;
 189       depth *= 6;
 190       break;
 191    case GL_TEXTURE_3D:
 192       assert(mt);
 193       depth = MAX2(mt->logical_depth0, 1);
 194       surftype = translate_tex_target(gl_target);
 195       break;
 196    case GL_TEXTURE_1D_ARRAY:
 197    case GL_TEXTURE_1D:
 198       if (brw->gen >= 9) {
 199          /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
 200           * textures but it does allow pretending it's a 2D texture
 201           * instead.
 202           */
 203          surftype = BRW_SURFACE_2D;
 204          break;
 205       }
 206       /* fallthrough */
 207    default:
 208       surftype = translate_tex_target(gl_target);
 209       break;
 210    }
 211
 212    min_array_element = irb ? irb->mt_layer : 0;
 213
 214    lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 215
 216    if (mt) {
 217       width = mt->logical_width0;
 218       height = mt->logical_height0;
 219    }
 220
 221    emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
 222                       brw_depth_writes_enabled(brw),
 223                       stencil_mt, ctx->Stencil._WriteEnabled,
 224                       hiz, width, height, depth, lod, min_array_element);
 225 }
 226
 227 /**
 228  * Should we set the PMA FIX ENABLE bit?
 229  *
 230  * To avoid unnecessary depth related stalls, we need to set this bit.
 231  * However, there is a very complicated formula which governs when it
 232  * is legal to do so.  This function computes that.
 233  *
 234  * See the documenation for the CACHE_MODE_1 register, bit 11.
 235  */
 236 static bool
 237 pma_fix_enable(const struct brw_context *brw)
 238 {
 239    const struct gl_context *ctx = &brw->ctx;
 240    /* BRW_NEW_FS_PROG_DATA */
 241    const struct brw_wm_prog_data *wm_prog_data =
 242       brw_wm_prog_data(brw->wm.base.prog_data);
 243    /* _NEW_BUFFERS */
 244    struct intel_renderbuffer *depth_irb =
 245       intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 246
 247    /* 3DSTATE_WM::ForceThreadDispatch is never used. */
 248    const bool wm_force_thread_dispatch = false;
 249
 250    /* 3DSTATE_RASTER::ForceSampleCount is never used. */
 251    const bool raster_force_sample_count_nonzero = false;
 252
 253    /* _NEW_BUFFERS:
 254     * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 255     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 256     */
 257    const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
 258
 259    /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2). */
 260    const bool edsc_not_preps = !wm_prog_data->early_fragment_tests;
 261
 262    /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
 263    const bool pixel_shader_valid = true;
 264
 265    /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 266     *   3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 267     *   3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 268     *   3DSTATE_WM_HZ_OP::StencilBufferClear)
 269     *
 270     * HiZ operations are done outside of the normal state upload, so they're
 271     * definitely not happening now.
 272     */
 273    const bool in_hiz_op = false;
 274
 275    /* _NEW_DEPTH:
 276     * DEPTH_STENCIL_STATE::DepthTestEnable
 277     */
 278    const bool depth_test_enabled = depth_irb && ctx->Depth.Test;
 279
 280    /* _NEW_DEPTH:
 281     * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 282     * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
 283     */
 284    const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
 285
 286    /* _NEW_STENCIL:
 287     * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
 288     * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
 289     * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
 290     */
 291    const bool stencil_writes_enabled = ctx->Stencil._WriteEnabled;
 292
 293    /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode != PSCDEPTH_OFF */
 294    const bool ps_computes_depth =
 295       wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
 296
 297    /* BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::PixelShaderKillsPixels
 298     * BRW_NEW_FS_PROG_DATA:     3DSTATE_PS_EXTRA::oMask Present to RenderTarget
 299     * _NEW_MULTISAMPLE:         3DSTATE_PS_BLEND::AlphaToCoverageEnable
 300     * _NEW_COLOR:               3DSTATE_PS_BLEND::AlphaTestEnable
 301     * _NEW_BUFFERS:             3DSTATE_PS_BLEND::AlphaTestEnable
 302     *                           3DSTATE_PS_BLEND::AlphaToCoverageEnable
 303     *
 304     * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
 305     * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
 306     */
 307    const bool kill_pixel =
 308       wm_prog_data->uses_kill ||
 309       wm_prog_data->uses_omask ||
 310       _mesa_is_alpha_test_enabled(ctx) ||
 311       _mesa_is_alpha_to_coverage_enabled(ctx);
 312
 313    /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
 314    return !wm_force_thread_dispatch &&
 315           !raster_force_sample_count_nonzero &&
 316           hiz_enabled &&
 317           edsc_not_preps &&
 318           pixel_shader_valid &&
 319           !in_hiz_op &&
 320           depth_test_enabled &&
 321           (ps_computes_depth ||
 322            (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
 323 }
 324
 325 void
 326 gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
 327 {
 328    struct gl_context *ctx = &brw->ctx;
 329
 330    /* If we haven't actually changed the value, bail now to avoid unnecessary
 331     * pipeline stalls and register writes.
 332     */
 333    if (brw->pma_stall_bits == pma_stall_bits)
 334       return;
 335
 336    brw->pma_stall_bits = pma_stall_bits;
 337
 338    /* According to the PIPE_CONTROL documentation, software should emit a
 339     * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
 340     * to the LRI.  If stencil buffer writes are enabled, then a Render Cache
 341     * Flush is also necessary.
 342     */
 343    const uint32_t render_cache_flush =
 344       ctx->Stencil._WriteEnabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
 345    brw_emit_pipe_control_flush(brw,
 346                                PIPE_CONTROL_CS_STALL |
 347                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 348                                render_cache_flush);
 349
 350    /* CACHE_MODE_1 is a non-privileged register. */
 351    BEGIN_BATCH(3);
 352    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 353    OUT_BATCH(GEN7_CACHE_MODE_1);
 354    OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
 355    ADVANCE_BATCH();
 356
 357    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 358     * Flush bits is often necessary.  We do it regardless because it's easier.
 359     * The render cache flush is also necessary if stencil writes are enabled.
 360     */
 361    brw_emit_pipe_control_flush(brw,
 362                                PIPE_CONTROL_DEPTH_STALL |
 363                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 364                                render_cache_flush);
 365
 366 }
 367
 368 static void
 369 gen8_emit_pma_stall_workaround(struct brw_context *brw)
 370 {
 371    uint32_t bits = 0;
 372
 373    if (brw->gen >= 9)
 374       return;
 375
 376    if (pma_fix_enable(brw))
 377       bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
 378
 379    gen8_write_pma_stall_bits(brw, bits);
 380 }
 381
 382 const struct brw_tracked_state gen8_pma_fix = {
 383    .dirty = {
 384       .mesa = _NEW_BUFFERS |
 385               _NEW_COLOR |
 386               _NEW_DEPTH |
 387               _NEW_MULTISAMPLE |
 388               _NEW_STENCIL,
 389       .brw = BRW_NEW_BLORP |
 390              BRW_NEW_FS_PROG_DATA,
 391    },
 392    .emit = gen8_emit_pma_stall_workaround
 393 };
 394
 395 /**
 396  * Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
 397  *
 398  * See the "Optimized Depth Buffer Clear and/or Stencil Buffer Clear" section
 399  * of the hardware documentation for details.
 400  */
 401 void
 402 gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 403               unsigned int level, unsigned int layer, enum blorp_hiz_op op)
 404 {
 405    if (op == BLORP_HIZ_OP_NONE)
 406       return;
 407
 408    /* Disable the PMA stall fix since we're about to do a HiZ operation. */
 409    if (brw->gen == 8)
 410       gen8_write_pma_stall_bits(brw, 0);
 411
 412    assert(mt->first_level == 0);
 413    assert(mt->logical_depth0 >= 1);
 414
 415    /* If we're operating on LOD 0, align to 8x4 to meet the alignment
 416     * requirements for most HiZ operations.  Otherwise, use the actual size
 417     * to allow the hardware to calculate the miplevel offsets correctly.
 418     */
 419    uint32_t surface_width  = ALIGN(mt->logical_width0,  level == 0 ? 8 : 1);
 420    uint32_t surface_height = ALIGN(mt->logical_height0, level == 0 ? 4 : 1);
 421
 422    /* From the documentation for 3DSTATE_WM_HZ_OP: "3DSTATE_MULTISAMPLE packet
 423     * must be used prior to this packet to change the Number of Multisamples.
 424     * This packet must not be used to change Number of Multisamples in a
 425     * rendering sequence."
 426     */
 427    if (brw->num_samples != mt->num_samples) {
 428       gen8_emit_3dstate_multisample(brw, mt->num_samples);
 429       brw->NewGLState |= _NEW_MULTISAMPLE;
 430    }
 431
 432    /* The basic algorithm is:
 433     * - If needed, emit 3DSTATE_{DEPTH,HIER_DEPTH,STENCIL}_BUFFER and
 434     *   3DSTATE_CLEAR_PARAMS packets to set up the relevant buffers.
 435     * - If needed, emit 3DSTATE_DRAWING_RECTANGLE.
 436     * - Emit 3DSTATE_WM_HZ_OP with a bit set for the particular operation.
 437     * - Do a special PIPE_CONTROL to trigger an implicit rectangle primitive.
 438     * - Emit 3DSTATE_WM_HZ_OP with no bits set to return to normal rendering.
 439     */
 440    emit_depth_packets(brw, mt,
 441                       brw_depth_format(brw, mt->format),
 442                       BRW_SURFACE_2D,
 443                       true, /* depth writes */
 444                       NULL, false, /* no stencil for now */
 445                       true, /* hiz */
 446                       surface_width,
 447                       surface_height,
 448                       mt->logical_depth0,
 449                       level,
 450                       layer); /* min_array_element */
 451
 452    /* Depth buffer clears and HiZ resolves must use an 8x4 aligned rectangle.
 453     * Note that intel_miptree_level_enable_hiz disables HiZ for miplevels > 0
 454     * which aren't 8x4 aligned, so expanding the size is safe - it'll just
 455     * draw into empty padding space.
 456     */
 457    unsigned rect_width = ALIGN(minify(mt->logical_width0, level), 8);
 458    unsigned rect_height = ALIGN(minify(mt->logical_height0, level), 4);
 459
 460    BEGIN_BATCH(4);
 461    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 462    OUT_BATCH(0);
 463    OUT_BATCH(((rect_width - 1) & 0xffff) | ((rect_height - 1) << 16));
 464    OUT_BATCH(0);
 465    ADVANCE_BATCH();
 466
 467    /* Emit 3DSTATE_WM_HZ_OP to override pipeline state for the particular
 468     * resolve or clear operation we want to perform.
 469     */
 470    uint32_t dw1 = 0;
 471
 472    switch (op) {
 473    case BLORP_HIZ_OP_DEPTH_RESOLVE:
 474       dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE;
 475       break;
 476    case BLORP_HIZ_OP_HIZ_RESOLVE:
 477       dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
 478       break;
 479    case BLORP_HIZ_OP_DEPTH_CLEAR:
 480       dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
 481
 482       /* The "Clear Rectangle X Max" (and Y Max) fields are exclusive,
 483        * rather than inclusive, and limited to 16383.  This means that
 484        * for a 16384x16384 render target, we would miss the last row
 485        * or column of pixels along the edge.
 486        *
 487        * To work around this, we have to set the "Full Surface Depth
 488        * and Stencil Clear" bit.  We can do this in all cases because
 489        * we always clear the full rectangle anyway.  We'll need to
 490        * change this if we ever add scissored clear support.
 491        */
 492       dw1 |= GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR;
 493       break;
 494    case BLORP_HIZ_OP_NONE:
 495       unreachable("Should not get here.");
 496    }
 497
 498    if (mt->num_samples > 0)
 499       dw1 |= SET_FIELD(ffs(mt->num_samples) - 1, GEN8_WM_HZ_NUM_SAMPLES);
 500
 501    BEGIN_BATCH(5);
 502    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 503    OUT_BATCH(dw1);
 504    OUT_BATCH(0);
 505    OUT_BATCH(SET_FIELD(rect_width, GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX) |
 506              SET_FIELD(rect_height, GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX));
 507    OUT_BATCH(SET_FIELD(0xFFFF, GEN8_WM_HZ_SAMPLE_MASK));
 508    ADVANCE_BATCH();
 509
 510    /* Emit a PIPE_CONTROL with "Post-Sync Operation" set to "Write Immediate
 511     * Data", and no other bits set.  This causes 3DSTATE_WM_HZ_OP's state to
 512     * take effect, and spawns a rectangle primitive.
 513     */
 514    brw_emit_pipe_control_write(brw,
 515                                PIPE_CONTROL_WRITE_IMMEDIATE,
 516                                brw->workaround_bo, 0, 0, 0);
 517
 518    /* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
 519    BEGIN_BATCH(5);
 520    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
 521    OUT_BATCH(0);
 522    OUT_BATCH(0);
 523    OUT_BATCH(0);
 524    OUT_BATCH(0);
 525    ADVANCE_BATCH();
 526
 527    /*
 528     * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
 529     *
 530     *  Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
 531     *  or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
 532     *  DEPTH_STALL bit and Depth FLUSH bits "set" before starting to render.
 533     *  DepthStall and DepthFlush are not needed between consecutive depth
 534     *  clear passes nor is it required if th e depth clear pass was done with
 535     *  "full_surf_clear" bit set in the 3DSTATE_WM_HZ_OP.
 536     *
 537     *  TODO: Such as the spec says, this could be conditional.
 538     */
 539    brw_emit_pipe_control_flush(brw,
 540                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 541                                PIPE_CONTROL_DEPTH_STALL);
 542
 543    /* Mark this buffer as needing a TC flush, as we've rendered to it. */
 544    brw_render_cache_set_add_bo(brw, mt->bo);
 545
 546    /* We've clobbered all of the depth packets, and the drawing rectangle,
 547     * so we need to ensure those packets are re-emitted before the next
 548     * primitive.
 549     *
 550     * Setting _NEW_DEPTH and _NEW_BUFFERS covers it, but is rather overkill.
 551     */
 552    brw->NewGLState |= _NEW_DEPTH | _NEW_BUFFERS;
 553 }