src/mesa/drivers/dri/i965/gen8_disable.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29 static void
  30 disable_stages(struct brw_context *brw)
  31 {
  32    BEGIN_BATCH(5);
  33    OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
  34    OUT_BATCH(0);
  35    OUT_BATCH(0);
  36    OUT_BATCH(0);
  37    OUT_BATCH(0);
  38    ADVANCE_BATCH();
  39
  40    /* Disable the HS Unit */
  41    BEGIN_BATCH(11);
  42    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));
  43    OUT_BATCH(0);
  44    OUT_BATCH(0);
  45    OUT_BATCH(0);
  46    OUT_BATCH(0);
  47    OUT_BATCH(0);
  48    OUT_BATCH(0);
  49    OUT_BATCH(0);
  50    OUT_BATCH(0);
  51    OUT_BATCH(0);
  52    OUT_BATCH(0);
  53    ADVANCE_BATCH();
  54
  55    BEGIN_BATCH(9);
  56    OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
  57    OUT_BATCH(0);
  58    OUT_BATCH(0);
  59    OUT_BATCH(0);
  60    OUT_BATCH(0);
  61    OUT_BATCH(0);
  62    OUT_BATCH(0);
  63    OUT_BATCH(0);
  64    OUT_BATCH(0);
  65    ADVANCE_BATCH();
  66
  67    BEGIN_BATCH(2);
  68    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
  69    OUT_BATCH(brw->hw_bt_pool.next_offset);
  70    ADVANCE_BATCH();
  71
  72    /* Disable the TE */
  73    BEGIN_BATCH(4);
  74    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
  75    OUT_BATCH(0);
  76    OUT_BATCH(0);
  77    OUT_BATCH(0);
  78    ADVANCE_BATCH();
  79
  80    /* Disable the DS Unit */
  81    BEGIN_BATCH(11);
  82    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (11 - 2));
  83    OUT_BATCH(0);
  84    OUT_BATCH(0);
  85    OUT_BATCH(0);
  86    OUT_BATCH(0);
  87    OUT_BATCH(0);
  88    OUT_BATCH(0);
  89    OUT_BATCH(0);
  90    OUT_BATCH(0);
  91    OUT_BATCH(0);
  92    OUT_BATCH(0);
  93    ADVANCE_BATCH();
  94
  95    int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
  96    BEGIN_BATCH(ds_pkt_len);
  97    OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
  98    for (int i = 0; i < ds_pkt_len - 1; i++)
  99       OUT_BATCH(0);
 100    ADVANCE_BATCH();
 101
 102    BEGIN_BATCH(2);
 103    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
 104    OUT_BATCH(brw->hw_bt_pool.next_offset);
 105    ADVANCE_BATCH();
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2));
 109    OUT_BATCH(0);
 110    ADVANCE_BATCH();
 111 }
 112
 113 const struct brw_tracked_state gen8_disable_stages = {
 114    .dirty = {
 115       .mesa  = 0,
 116       .brw   = BRW_NEW_CONTEXT,
 117    },
 118    .emit = disable_stages,
 119 };