2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/glheader.h"
25 #include "main/bufferobj.h"
26 #include "main/context.h"
27 #include "main/enums.h"
28 #include "main/macros.h"
31 #include "brw_defines.h"
32 #include "brw_context.h"
33 #include "brw_state.h"
35 #include "intel_batchbuffer.h"
36 #include "intel_buffer_objects.h"
39 gen8_emit_vertices(struct brw_context
*brw
)
41 struct gl_context
*ctx
= &brw
->ctx
;
42 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
44 brw_prepare_vertices(brw
);
45 brw_prepare_shader_draw_parameters(brw
);
47 if (brw
->vs
.prog_data
->uses_vertexid
|| brw
->vs
.prog_data
->uses_instanceid
) {
48 unsigned vue
= brw
->vb
.nr_enabled
;
50 WARN_ONCE(brw
->vs
.prog_data
->inputs_read
& VERT_BIT_EDGEFLAG
,
51 "Using VID/IID with edgeflags, need to reorder the "
54 "Trying to insert VID/IID past 33rd vertex element, "
55 "need to reorder the vertex attrbutes.");
58 if (brw
->vs
.prog_data
->uses_vertexid
) {
59 dw1
|= GEN8_SGVS_ENABLE_VERTEX_ID
|
60 (2 << GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT
) | /* .z channel */
61 (vue
<< GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT
);
64 if (brw
->vs
.prog_data
->uses_instanceid
) {
65 dw1
|= GEN8_SGVS_ENABLE_INSTANCE_ID
|
66 (3 << GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT
) | /* .w channel */
67 (vue
<< GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT
);
71 OUT_BATCH(_3DSTATE_VF_SGVS
<< 16 | (2 - 2));
76 OUT_BATCH(_3DSTATE_VF_INSTANCING
<< 16 | (3 - 2));
77 OUT_BATCH(brw
->vb
.nr_buffers
| GEN8_VF_INSTANCING_ENABLE
);
82 OUT_BATCH(_3DSTATE_VF_SGVS
<< 16 | (2 - 2));
87 /* If the VS doesn't read any inputs (calculating vertex position from
88 * a state variable for some reason, for example), emit a single pad
89 * VERTEX_ELEMENT struct and bail.
91 * The stale VB state stays in place, but they don't do anything unless
92 * a VE loads from them.
94 if (brw
->vb
.nr_enabled
== 0) {
96 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (3 - 2));
97 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT
) |
99 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
100 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
101 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
102 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
103 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
104 (BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
));
109 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
110 unsigned nr_buffers
= brw
->vb
.nr_buffers
+ brw
->vs
.prog_data
->uses_vertexid
;
112 assert(nr_buffers
<= 33);
114 BEGIN_BATCH(1 + 4 * nr_buffers
);
115 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (4 * nr_buffers
- 1));
116 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
117 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
120 dw0
|= i
<< GEN6_VB0_INDEX_SHIFT
;
121 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
122 dw0
|= buffer
->stride
<< BRW_VB0_PITCH_SHIFT
;
123 dw0
|= mocs_wb
<< 16;
126 OUT_RELOC64(buffer
->bo
, I915_GEM_DOMAIN_VERTEX
, 0, buffer
->offset
);
127 OUT_BATCH(buffer
->bo
->size
);
130 if (brw
->vs
.prog_data
->uses_vertexid
) {
131 OUT_BATCH(brw
->vb
.nr_buffers
<< GEN6_VB0_INDEX_SHIFT
|
132 GEN7_VB0_ADDRESS_MODIFYENABLE
|
134 OUT_RELOC64(brw
->draw
.draw_params_bo
, I915_GEM_DOMAIN_VERTEX
, 0,
135 brw
->draw
.draw_params_offset
);
136 OUT_BATCH(brw
->draw
.draw_params_bo
->size
);
141 unsigned nr_elements
= brw
->vb
.nr_enabled
+ brw
->vs
.prog_data
->uses_vertexid
;
143 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
144 * presumably for VertexID/InstanceID.
146 assert(nr_elements
<= 34);
148 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
150 BEGIN_BATCH(1 + nr_elements
* 2);
151 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (2 * nr_elements
- 1));
152 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
153 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
154 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
155 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
156 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
157 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_SRC
;
158 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_SRC
;
160 /* The gen4 driver expects edgeflag to come in as a float, and passes
161 * that float on to the tests in the clipper. Mesa's current vertex
162 * attribute value for EdgeFlag is stored as a float, which works out.
163 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
164 * integer ubyte. Just rewrite that to convert to a float.
166 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
167 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
168 * of in the VUE. We have to upload it sideband as the last vertex
169 * element according to the B-Spec.
171 gen6_edgeflag_input
= input
;
175 switch (input
->glarray
->Size
) {
176 case 0: comp0
= BRW_VE1_COMPONENT_STORE_0
;
177 case 1: comp1
= BRW_VE1_COMPONENT_STORE_0
;
178 case 2: comp2
= BRW_VE1_COMPONENT_STORE_0
;
179 case 3: comp3
= input
->glarray
->Integer
? BRW_VE1_COMPONENT_STORE_1_INT
180 : BRW_VE1_COMPONENT_STORE_1_FLT
;
184 OUT_BATCH((input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
186 (format
<< BRW_VE0_FORMAT_SHIFT
) |
187 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
189 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
190 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
191 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
192 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
));
195 if (gen6_edgeflag_input
) {
197 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
199 OUT_BATCH((gen6_edgeflag_input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
201 GEN6_VE0_EDGE_FLAG_ENABLE
|
202 (format
<< BRW_VE0_FORMAT_SHIFT
) |
203 (gen6_edgeflag_input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
204 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
205 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
206 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
207 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
));
210 if (brw
->vs
.prog_data
->uses_vertexid
) {
211 OUT_BATCH(GEN6_VE0_VALID
|
212 brw
->vb
.nr_buffers
<< GEN6_VE0_INDEX_SHIFT
|
213 BRW_SURFACEFORMAT_R32_UINT
<< BRW_VE0_FORMAT_SHIFT
);
214 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
215 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
216 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
217 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
));
221 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
222 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
223 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
226 OUT_BATCH(_3DSTATE_VF_INSTANCING
<< 16 | (3 - 2));
227 OUT_BATCH(i
| (buffer
->step_rate
? GEN8_VF_INSTANCING_ENABLE
: 0));
228 OUT_BATCH(buffer
->step_rate
);
233 const struct brw_tracked_state gen8_vertices
= {
235 .mesa
= _NEW_POLYGON
,
236 .brw
= BRW_NEW_BATCH
|
238 BRW_NEW_VS_PROG_DATA
,
240 .emit
= gen8_emit_vertices
,
244 gen8_emit_index_buffer(struct brw_context
*brw
)
246 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
247 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
249 if (index_buffer
== NULL
)
253 OUT_BATCH(CMD_INDEX_BUFFER
<< 16 | (5 - 2));
254 OUT_BATCH(brw_get_index_type(index_buffer
->type
) | mocs_wb
);
255 OUT_RELOC64(brw
->ib
.bo
, I915_GEM_DOMAIN_VERTEX
, 0, 0);
256 OUT_BATCH(brw
->ib
.bo
->size
);
260 const struct brw_tracked_state gen8_index_buffer
= {
263 .brw
= BRW_NEW_BATCH
|
264 BRW_NEW_INDEX_BUFFER
,
266 .emit
= gen8_emit_index_buffer
,
270 gen8_emit_vf_topology(struct brw_context
*brw
)
273 OUT_BATCH(_3DSTATE_VF_TOPOLOGY
<< 16 | (2 - 2));
274 OUT_BATCH(brw
->primitive
);
278 const struct brw_tracked_state gen8_vf_topology
= {
281 .brw
= BRW_NEW_PRIMITIVE
,
283 .emit
= gen8_emit_vf_topology
,