2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/glheader.h"
25 #include "main/bufferobj.h"
26 #include "main/context.h"
27 #include "main/enums.h"
28 #include "main/macros.h"
31 #include "brw_defines.h"
32 #include "brw_context.h"
33 #include "brw_state.h"
35 #include "intel_batchbuffer.h"
36 #include "intel_buffer_objects.h"
39 gen8_emit_vertices(struct brw_context
*brw
)
41 struct gl_context
*ctx
= &brw
->ctx
;
43 brw_prepare_vertices(brw
);
45 if (brw
->vs
.prog_data
->uses_vertexid
) {
46 unsigned vue
= brw
->vb
.nr_enabled
;
48 WARN_ONCE(brw
->vs
.prog_data
->inputs_read
& VERT_BIT_EDGEFLAG
,
49 "Using VID/IID with edgeflags, need to reorder the "
52 "Trying to insert VID/IID past 33rd vertex element, "
53 "need to reorder the vertex attrbutes.");
56 OUT_BATCH(_3DSTATE_VF_SGVS
<< 16 | (2 - 2));
57 OUT_BATCH(GEN8_SGVS_ENABLE_VERTEX_ID
|
58 (0 << GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT
) | /* .x channel */
59 (vue
<< GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT
) |
60 GEN8_SGVS_ENABLE_INSTANCE_ID
|
61 (1 << GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT
) | /* .y channel */
62 (vue
<< GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT
));
66 OUT_BATCH(_3DSTATE_VF_SGVS
<< 16 | (2 - 2));
71 /* If the VS doesn't read any inputs (calculating vertex position from
72 * a state variable for some reason, for example), emit a single pad
73 * VERTEX_ELEMENT struct and bail.
75 * The stale VB state stays in place, but they don't do anything unless
76 * a VE loads from them.
78 if (brw
->vb
.nr_enabled
== 0) {
80 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (3 - 2));
81 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT
) |
83 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
84 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
85 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
86 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
87 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
88 (BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
));
93 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
94 if (brw
->vb
.nr_buffers
) {
95 assert(brw
->vb
.nr_buffers
<= 33);
97 BEGIN_BATCH(1 + 4*brw
->vb
.nr_buffers
);
98 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (4*brw
->vb
.nr_buffers
- 1));
99 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
100 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
103 dw0
|= i
<< GEN6_VB0_INDEX_SHIFT
;
104 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
105 dw0
|= buffer
->stride
<< BRW_VB0_PITCH_SHIFT
;
106 dw0
|= BDW_MOCS_WB
<< 16;
109 OUT_RELOC64(buffer
->bo
, I915_GEM_DOMAIN_VERTEX
, 0, buffer
->offset
);
110 OUT_BATCH(buffer
->bo
->size
);
115 unsigned nr_elements
= brw
->vb
.nr_enabled
;
117 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
118 * presumably for VertexID/InstanceID.
120 assert(nr_elements
<= 34);
122 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
124 BEGIN_BATCH(1 + nr_elements
* 2);
125 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (2 * nr_elements
- 1));
126 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
127 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
128 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
129 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
130 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
131 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_SRC
;
132 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_SRC
;
134 /* The gen4 driver expects edgeflag to come in as a float, and passes
135 * that float on to the tests in the clipper. Mesa's current vertex
136 * attribute value for EdgeFlag is stored as a float, which works out.
137 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
138 * integer ubyte. Just rewrite that to convert to a float.
140 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
141 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
142 * of in the VUE. We have to upload it sideband as the last vertex
143 * element according to the B-Spec.
145 gen6_edgeflag_input
= input
;
149 switch (input
->glarray
->Size
) {
150 case 0: comp0
= BRW_VE1_COMPONENT_STORE_0
;
151 case 1: comp1
= BRW_VE1_COMPONENT_STORE_0
;
152 case 2: comp2
= BRW_VE1_COMPONENT_STORE_0
;
153 case 3: comp3
= input
->glarray
->Integer
? BRW_VE1_COMPONENT_STORE_1_INT
154 : BRW_VE1_COMPONENT_STORE_1_FLT
;
158 OUT_BATCH((input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
160 (format
<< BRW_VE0_FORMAT_SHIFT
) |
161 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
163 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
164 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
165 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
166 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
));
169 if (gen6_edgeflag_input
) {
171 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
173 OUT_BATCH((gen6_edgeflag_input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
175 GEN6_VE0_EDGE_FLAG_ENABLE
|
176 (format
<< BRW_VE0_FORMAT_SHIFT
) |
177 (gen6_edgeflag_input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
178 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
179 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
180 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
181 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
));
185 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
186 const struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
187 const struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[input
->buffer
];
190 OUT_BATCH(_3DSTATE_VF_INSTANCING
<< 16 | (3 - 2));
191 OUT_BATCH(i
| (buffer
->step_rate
? GEN8_VF_INSTANCING_ENABLE
: 0));
192 OUT_BATCH(buffer
->step_rate
);
197 const struct brw_tracked_state gen8_vertices
= {
199 .mesa
= _NEW_POLYGON
,
200 .brw
= BRW_NEW_BATCH
| BRW_NEW_VERTICES
,
201 .cache
= CACHE_NEW_VS_PROG
,
203 .emit
= gen8_emit_vertices
,
207 gen8_emit_index_buffer(struct brw_context
*brw
)
209 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
211 if (index_buffer
== NULL
)
215 OUT_BATCH(CMD_INDEX_BUFFER
<< 16 | (5 - 2));
216 OUT_BATCH(brw_get_index_type(index_buffer
->type
) << 8 | BDW_MOCS_WB
);
217 OUT_RELOC64(brw
->ib
.bo
, I915_GEM_DOMAIN_VERTEX
, 0, 0);
218 OUT_BATCH(brw
->ib
.bo
->size
);
222 const struct brw_tracked_state gen8_index_buffer
= {
225 .brw
= BRW_NEW_BATCH
| BRW_NEW_INDEX_BUFFER
,
228 .emit
= gen8_emit_index_buffer
,
232 gen8_emit_vf_topology(struct brw_context
*brw
)
235 OUT_BATCH(_3DSTATE_VF_TOPOLOGY
<< 16 | (2 - 2));
236 OUT_BATCH(brw
->primitive
);
240 const struct brw_tracked_state gen8_vf_topology
= {
243 .brw
= BRW_NEW_PRIMITIVE
,
246 .emit
= gen8_emit_vf_topology
,