src/mesa/drivers/dri/i965/gen8_draw_upload.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/bufferobj.h"
  25 #include "main/context.h"
  26 #include "main/enums.h"
  27 #include "main/macros.h"
  28
  29 #include "brw_draw.h"
  30 #include "brw_defines.h"
  31 #include "brw_context.h"
  32 #include "brw_state.h"
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_buffer_objects.h"
  36
  37 static void
  38 gen8_emit_vertices(struct brw_context *brw)
  39 {
  40    struct gl_context *ctx = &brw->ctx;
  41    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  42    bool uses_edge_flag;
  43
  44    brw_prepare_vertices(brw);
  45    brw_prepare_shader_draw_parameters(brw);
  46
  47    uses_edge_flag = (ctx->Polygon.FrontMode != GL_FILL ||
  48                      ctx->Polygon.BackMode != GL_FILL);
  49
  50    if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid) {
  51       unsigned vue = brw->vb.nr_enabled;
  52
  53       /* The element for the edge flags must always be last, so we have to
  54        * insert the SGVS before it in that case.
  55        */
  56       if (uses_edge_flag) {
  57          assert(vue > 0);
  58          vue--;
  59       }
  60
  61       WARN_ONCE(vue >= 33,
  62                 "Trying to insert VID/IID past 33rd vertex element, "
  63                 "need to reorder the vertex attrbutes.");
  64
  65       unsigned dw1 = 0;
  66       if (brw->vs.prog_data->uses_vertexid) {
  67          dw1 |= GEN8_SGVS_ENABLE_VERTEX_ID |
  68                 (2 << GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT) |  /* .z channel */
  69                 (vue << GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT);
  70       }
  71
  72       if (brw->vs.prog_data->uses_instanceid) {
  73          dw1 |= GEN8_SGVS_ENABLE_INSTANCE_ID |
  74                 (3 << GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT) | /* .w channel */
  75                 (vue << GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT);
  76       }
  77
  78       BEGIN_BATCH(2);
  79       OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
  80       OUT_BATCH(dw1);
  81       ADVANCE_BATCH();
  82
  83       BEGIN_BATCH(3);
  84       OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
  85       OUT_BATCH(vue | GEN8_VF_INSTANCING_ENABLE);
  86       OUT_BATCH(0);
  87       ADVANCE_BATCH();
  88    } else {
  89       BEGIN_BATCH(2);
  90       OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
  91       OUT_BATCH(0);
  92       ADVANCE_BATCH();
  93    }
  94
  95    /* If the VS doesn't read any inputs (calculating vertex position from
  96     * a state variable for some reason, for example), emit a single pad
  97     * VERTEX_ELEMENT struct and bail.
  98     *
  99     * The stale VB state stays in place, but they don't do anything unless
 100     * a VE loads from them.
 101     */
 102    if (brw->vb.nr_enabled == 0) {
 103       BEGIN_BATCH(3);
 104       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (3 - 2));
 105       OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
 106                 GEN6_VE0_VALID |
 107                 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 108                 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 109       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 110                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 111                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 112                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
 113       ADVANCE_BATCH();
 114       return;
 115    }
 116
 117    /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
 118    const bool uses_draw_params =
 119       brw->vs.prog_data->uses_basevertex ||
 120       brw->vs.prog_data->uses_baseinstance;
 121    const unsigned nr_buffers = brw->vb.nr_buffers +
 122       uses_draw_params + brw->vs.prog_data->uses_drawid;
 123
 124    if (nr_buffers) {
 125       assert(nr_buffers <= 33);
 126
 127       BEGIN_BATCH(1 + 4 * nr_buffers);
 128       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
 129       for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
 130          struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
 131          uint32_t dw0 = 0;
 132
 133          dw0 |= i << GEN6_VB0_INDEX_SHIFT;
 134          dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 135          dw0 |= buffer->stride << BRW_VB0_PITCH_SHIFT;
 136          dw0 |= mocs_wb << 16;
 137
 138          OUT_BATCH(dw0);
 139          OUT_RELOC64(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
 140          OUT_BATCH(buffer->bo->size);
 141       }
 142
 143       if (uses_draw_params) {
 144          OUT_BATCH(brw->vb.nr_buffers << GEN6_VB0_INDEX_SHIFT |
 145                    GEN7_VB0_ADDRESS_MODIFYENABLE |
 146                    mocs_wb << 16);
 147          OUT_RELOC64(brw->draw.draw_params_bo, I915_GEM_DOMAIN_VERTEX, 0,
 148                      brw->draw.draw_params_offset);
 149          OUT_BATCH(brw->draw.draw_params_bo->size);
 150       }
 151
 152       if (brw->vs.prog_data->uses_drawid) {
 153          OUT_BATCH((brw->vb.nr_buffers + 1) << GEN6_VB0_INDEX_SHIFT |
 154                    GEN7_VB0_ADDRESS_MODIFYENABLE |
 155                    mocs_wb << 16);
 156          OUT_RELOC64(brw->draw.draw_id_bo, I915_GEM_DOMAIN_VERTEX, 0,
 157                      brw->draw.draw_id_offset);
 158          OUT_BATCH(brw->draw.draw_id_bo->size);
 159       }
 160       ADVANCE_BATCH();
 161    }
 162
 163    /* Normally we don't need an element for the SGVS attribute because the
 164     * 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
 165     * element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
 166     * we're using draw parameters then we need an element for the those
 167     * values.  Additionally if there is an edge flag element then the SGVS
 168     * can't be inserted past that so we need a dummy element to ensure that
 169     * the edge flag is the last one.
 170     */
 171    const bool needs_sgvs_element = (brw->vs.prog_data->uses_basevertex ||
 172                                     brw->vs.prog_data->uses_baseinstance ||
 173                                     ((brw->vs.prog_data->uses_instanceid ||
 174                                       brw->vs.prog_data->uses_vertexid) &&
 175                                      uses_edge_flag));
 176    const unsigned nr_elements =
 177       brw->vb.nr_enabled + needs_sgvs_element + brw->vs.prog_data->uses_drawid;
 178
 179    /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
 180     * presumably for VertexID/InstanceID.
 181     */
 182    assert(nr_elements <= 34);
 183
 184    struct brw_vertex_element *gen6_edgeflag_input = NULL;
 185
 186    BEGIN_BATCH(1 + nr_elements * 2);
 187    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
 188    for (unsigned i = 0; i < brw->vb.nr_enabled; i++) {
 189       struct brw_vertex_element *input = brw->vb.enabled[i];
 190       uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
 191       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 192       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 193       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
 194       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
 195
 196       /* The gen4 driver expects edgeflag to come in as a float, and passes
 197        * that float on to the tests in the clipper.  Mesa's current vertex
 198        * attribute value for EdgeFlag is stored as a float, which works out.
 199        * glEdgeFlagPointer, on the other hand, gives us an unnormalized
 200        * integer ubyte.  Just rewrite that to convert to a float.
 201        */
 202       if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
 203          /* Gen6+ passes edgeflag as sideband along with the vertex, instead
 204           * of in the VUE.  We have to upload it sideband as the last vertex
 205           * element according to the B-Spec.
 206           */
 207          gen6_edgeflag_input = input;
 208          continue;
 209       }
 210
 211       switch (input->glarray->Size) {
 212       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
 213       case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
 214       case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
 215       case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
 216                                               : BRW_VE1_COMPONENT_STORE_1_FLT;
 217          break;
 218       }
 219
 220       OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
 221                 GEN6_VE0_VALID |
 222                 (format << BRW_VE0_FORMAT_SHIFT) |
 223                 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 224
 225       OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 226                 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 227                 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 228                 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
 229    }
 230
 231    if (needs_sgvs_element) {
 232       if (brw->vs.prog_data->uses_basevertex ||
 233           brw->vs.prog_data->uses_baseinstance) {
 234          OUT_BATCH(GEN6_VE0_VALID |
 235                    brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
 236                    BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT);
 237          OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 238                    (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT) |
 239                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 240                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 241       } else {
 242          OUT_BATCH(GEN6_VE0_VALID);
 243          OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 244                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 245                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 246                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 247       }
 248    }
 249
 250    if (brw->vs.prog_data->uses_drawid) {
 251       OUT_BATCH(GEN6_VE0_VALID |
 252                 ((brw->vb.nr_buffers + 1) << GEN6_VE0_INDEX_SHIFT) |
 253                 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT));
 254       OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 255                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 256                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 257                    (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 258    }
 259
 260    if (gen6_edgeflag_input) {
 261       uint32_t format =
 262          brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
 263
 264       OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
 265                 GEN6_VE0_VALID |
 266                 GEN6_VE0_EDGE_FLAG_ENABLE |
 267                 (format << BRW_VE0_FORMAT_SHIFT) |
 268                 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 269       OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 270                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 271                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 272                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 273    }
 274    ADVANCE_BATCH();
 275
 276    for (unsigned i = 0, j = 0; i < brw->vb.nr_enabled; i++) {
 277       const struct brw_vertex_element *input = brw->vb.enabled[i];
 278       const struct brw_vertex_buffer *buffer = &brw->vb.buffers[input->buffer];
 279       unsigned element_index;
 280
 281       /* The edge flag element is reordered to be the last one in the code
 282        * above so we need to compensate for that in the element indices used
 283        * below.
 284        */
 285       if (input == gen6_edgeflag_input)
 286          element_index = nr_elements - 1;
 287       else
 288          element_index = j++;
 289
 290       BEGIN_BATCH(3);
 291       OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
 292       OUT_BATCH(element_index |
 293                 (buffer->step_rate ? GEN8_VF_INSTANCING_ENABLE : 0));
 294       OUT_BATCH(buffer->step_rate);
 295       ADVANCE_BATCH();
 296    }
 297
 298    if (brw->vs.prog_data->uses_drawid) {
 299       const unsigned element = brw->vb.nr_enabled + needs_sgvs_element;
 300       BEGIN_BATCH(3);
 301       OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
 302       OUT_BATCH(element);
 303       OUT_BATCH(0);
 304       ADVANCE_BATCH();
 305    }
 306 }
 307
 308 const struct brw_tracked_state gen8_vertices = {
 309    .dirty = {
 310       .mesa = _NEW_POLYGON,
 311       .brw = BRW_NEW_BATCH |
 312              BRW_NEW_BLORP |
 313              BRW_NEW_VERTICES |
 314              BRW_NEW_VS_PROG_DATA,
 315    },
 316    .emit = gen8_emit_vertices,
 317 };
 318
 319 static void
 320 gen8_emit_index_buffer(struct brw_context *brw)
 321 {
 322    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 323    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 324
 325    if (index_buffer == NULL)
 326       return;
 327
 328    BEGIN_BATCH(5);
 329    OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
 330    OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
 331    OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
 332    OUT_BATCH(brw->ib.bo->size);
 333    ADVANCE_BATCH();
 334 }
 335
 336 const struct brw_tracked_state gen8_index_buffer = {
 337    .dirty = {
 338       .mesa = 0,
 339       .brw = BRW_NEW_BATCH |
 340              BRW_NEW_BLORP |
 341              BRW_NEW_INDEX_BUFFER,
 342    },
 343    .emit = gen8_emit_index_buffer,
 344 };
 345
 346 static void
 347 gen8_emit_vf_topology(struct brw_context *brw)
 348 {
 349    BEGIN_BATCH(2);
 350    OUT_BATCH(_3DSTATE_VF_TOPOLOGY << 16 | (2 - 2));
 351    OUT_BATCH(brw->primitive);
 352    ADVANCE_BATCH();
 353 }
 354
 355 const struct brw_tracked_state gen8_vf_topology = {
 356    .dirty = {
 357       .mesa = 0,
 358       .brw = BRW_NEW_BLORP |
 359              BRW_NEW_PRIMITIVE,
 360    },
 361    .emit = gen8_emit_vf_topology,
 362 };