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i965/fs: Use next_insn_offset rather than nr_insn.
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_fs_generator.cpp
1 /*
2 * Copyright © 2010, 2011, 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file gen8_fs_generate.cpp
25 *
26 * Code generation for Gen8+ hardware.
27 */
28
29 extern "C" {
30 #include "main/macros.h"
31 #include "brw_context.h"
32 } /* extern "C" */
33
34 #include "brw_fs.h"
35 #include "brw_cfg.h"
36 #include "glsl/ir_print_visitor.h"
37
38 gen8_fs_generator::gen8_fs_generator(struct brw_context *brw,
39 void *mem_ctx,
40 const struct brw_wm_prog_key *key,
41 struct brw_wm_prog_data *prog_data,
42 struct gl_shader_program *shader_prog,
43 struct gl_fragment_program *fp,
44 bool dual_source_output)
45 : gen8_generator(brw, shader_prog, fp ? &fp->Base : NULL, mem_ctx),
46 key(key), prog_data(prog_data),
47 fp(fp), dual_source_output(dual_source_output)
48 {
49 }
50
51 gen8_fs_generator::~gen8_fs_generator()
52 {
53 }
54
55 void
56 gen8_fs_generator::generate_fb_write(fs_inst *ir)
57 {
58 /* Disable the discard condition while setting up the header. */
59 default_state.predicate = BRW_PREDICATE_NONE;
60 default_state.predicate_inverse = false;
61 default_state.flag_subreg_nr = 0;
62
63 if (ir->header_present) {
64 /* The GPU will use the predicate on SENDC, unless the header is present.
65 */
66 if (fp && fp->UsesKill) {
67 gen8_instruction *mov =
68 MOV(retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW),
69 brw_flag_reg(0, 1));
70 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
71 }
72
73 gen8_instruction *mov =
74 MOV_RAW(brw_message_reg(ir->base_mrf), brw_vec8_grf(0, 0));
75 gen8_set_exec_size(mov, BRW_EXECUTE_16);
76
77 if (ir->target > 0 && key->replicate_alpha) {
78 /* Set "Source0 Alpha Present to RenderTarget" bit in the header. */
79 gen8_instruction *inst =
80 OR(get_element_ud(brw_message_reg(ir->base_mrf), 0),
81 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
82 brw_imm_ud(1 << 11));
83 gen8_set_mask_control(inst, BRW_MASK_DISABLE);
84 }
85
86 if (ir->target > 0) {
87 /* Set the render target index for choosing BLEND_STATE. */
88 MOV_RAW(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2),
89 brw_imm_ud(ir->target));
90 }
91 }
92
93 /* Set the predicate back to get the conditional write if necessary for
94 * discards.
95 */
96 default_state.predicate = ir->predicate;
97 default_state.predicate_inverse = ir->predicate_inverse;
98 default_state.flag_subreg_nr = ir->flag_subreg;
99
100 gen8_instruction *inst = next_inst(BRW_OPCODE_SENDC);
101 gen8_set_dst(brw, inst, retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW));
102 gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
103
104 /* Set up the "Message Specific Control" bits for the Data Port Message
105 * Descriptor. These are documented in the "Render Target Write" message's
106 * "Message Descriptor" documentation (vol5c.2).
107 */
108 uint32_t msg_type;
109 /* Set the Message Type */
110 if (this->dual_source_output)
111 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
112 else if (dispatch_width == 16)
113 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
114 else
115 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
116
117 uint32_t msg_control = msg_type;
118
119 /* "Last Render Target Select" must be set on all writes to the last of
120 * the render targets (if using MRT), or always for a single RT scenario.
121 */
122 if ((ir->target == key->nr_color_regions - 1) || !key->nr_color_regions)
123 msg_control |= (1 << 4); /* Last Render Target Select */
124
125 uint32_t surf_index =
126 prog_data->binding_table.render_target_start + ir->target;
127
128 gen8_set_dp_message(brw, inst,
129 GEN6_SFID_DATAPORT_RENDER_CACHE,
130 surf_index,
131 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
132 msg_control,
133 ir->mlen,
134 0,
135 ir->header_present,
136 ir->eot);
137
138 brw_mark_surface_used(&prog_data->base, surf_index);
139 }
140
141 void
142 gen8_fs_generator::generate_linterp(fs_inst *inst,
143 struct brw_reg dst,
144 struct brw_reg *src)
145 {
146 struct brw_reg delta_x = src[0];
147 struct brw_reg delta_y = src[1];
148 struct brw_reg interp = src[2];
149
150 (void) delta_y;
151 assert(delta_y.nr == delta_x.nr + 1);
152 PLN(dst, interp, delta_x);
153 }
154
155 void
156 gen8_fs_generator::generate_tex(fs_inst *ir,
157 struct brw_reg dst,
158 struct brw_reg src)
159 {
160 int msg_type = -1;
161 int rlen = 4;
162 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
163
164 assert(src.file == BRW_GENERAL_REGISTER_FILE);
165
166 if (dispatch_width == 16 && !ir->force_uncompressed && !ir->force_sechalf)
167 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
168
169 switch (ir->opcode) {
170 case SHADER_OPCODE_TEX:
171 if (ir->shadow_compare) {
172 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
173 } else {
174 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
175 }
176 break;
177 case FS_OPCODE_TXB:
178 if (ir->shadow_compare) {
179 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
180 } else {
181 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
182 }
183 break;
184 case SHADER_OPCODE_TXL:
185 if (ir->shadow_compare) {
186 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
187 } else {
188 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
189 }
190 break;
191 case SHADER_OPCODE_TXS:
192 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
193 break;
194 case SHADER_OPCODE_TXD:
195 if (ir->shadow_compare) {
196 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
197 } else {
198 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
199 }
200 break;
201 case SHADER_OPCODE_TXF:
202 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
203 break;
204 case SHADER_OPCODE_TXF_CMS:
205 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
206 break;
207 case SHADER_OPCODE_TXF_UMS:
208 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
209 break;
210 case SHADER_OPCODE_TXF_MCS:
211 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
212 break;
213 case SHADER_OPCODE_LOD:
214 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
215 break;
216 case SHADER_OPCODE_TG4:
217 if (ir->shadow_compare) {
218 assert(brw->gen >= 7);
219 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
220 } else {
221 assert(brw->gen >= 6);
222 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
223 }
224 break;
225 case SHADER_OPCODE_TG4_OFFSET:
226 assert(brw->gen >= 7);
227 if (ir->shadow_compare) {
228 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
229 } else {
230 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
231 }
232 break;
233 default:
234 assert(!"not reached");
235 break;
236 }
237 assert(msg_type != -1);
238
239 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
240 rlen = 8;
241 dst = vec16(dst);
242 }
243
244 if (ir->header_present) {
245 /* The send-from-GRF for SIMD16 texturing with a header has an extra
246 * hardware register allocated to it, which we need to skip over (since
247 * our coordinates in the payload are in the even-numbered registers,
248 * and the header comes right before the first one.
249 */
250 if (dispatch_width == 16)
251 src.nr++;
252
253 unsigned save_exec_size = default_state.exec_size;
254 default_state.exec_size = BRW_EXECUTE_8;
255
256 MOV_RAW(src, brw_vec8_grf(0, 0));
257
258 if (ir->texture_offset) {
259 /* Set the texel offset bits. */
260 MOV_RAW(retype(brw_vec1_grf(src.nr, 2), BRW_REGISTER_TYPE_UD),
261 brw_imm_ud(ir->texture_offset));
262 }
263
264 if (ir->sampler >= 16) {
265 /* The "Sampler Index" field can only store values between 0 and 15.
266 * However, we can add an offset to the "Sampler State Pointer"
267 * field, effectively selecting a different set of 16 samplers.
268 *
269 * The "Sampler State Pointer" needs to be aligned to a 32-byte
270 * offset, and each sampler state is only 16-bytes, so we can't
271 * exclusively use the offset - we have to use both.
272 */
273 gen8_instruction *add =
274 ADD(get_element_ud(src, 3),
275 get_element_ud(brw_vec8_grf(0, 0), 3),
276 brw_imm_ud(16 * (ir->sampler / 16) *
277 sizeof(gen7_sampler_state)));
278 gen8_set_mask_control(add, BRW_MASK_DISABLE);
279 }
280
281 default_state.exec_size = save_exec_size;
282 }
283
284 uint32_t surf_index =
285 prog_data->base.binding_table.texture_start + ir->sampler;
286
287 gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
288 gen8_set_dst(brw, inst, dst);
289 gen8_set_src0(brw, inst, src);
290 gen8_set_sampler_message(brw, inst,
291 surf_index,
292 ir->sampler % 16,
293 msg_type,
294 rlen,
295 ir->mlen,
296 ir->header_present,
297 simd_mode);
298
299 brw_mark_surface_used(&prog_data->base, surf_index);
300 }
301
302
303 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
304 * looking like:
305 *
306 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
307 *
308 * and we're trying to produce:
309 *
310 * DDX DDY
311 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
312 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
313 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
314 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
315 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
316 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
317 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
318 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
319 *
320 * and add another set of two more subspans if in 16-pixel dispatch mode.
321 *
322 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
323 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
324 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
325 * between each other. We could probably do it like ddx and swizzle the right
326 * order later, but bail for now and just produce
327 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
328 */
329 void
330 gen8_fs_generator::generate_ddx(fs_inst *inst,
331 struct brw_reg dst,
332 struct brw_reg src)
333 {
334 unsigned vstride, width;
335
336 if (key->high_quality_derivatives) {
337 /* Produce accurate derivatives. */
338 vstride = BRW_VERTICAL_STRIDE_2;
339 width = BRW_WIDTH_2;
340 } else {
341 /* Replicate the derivative at the top-left pixel to other pixels. */
342 vstride = BRW_VERTICAL_STRIDE_4;
343 width = BRW_WIDTH_4;
344 }
345
346 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
347 BRW_REGISTER_TYPE_F,
348 vstride,
349 width,
350 BRW_HORIZONTAL_STRIDE_0,
351 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
352 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
353 BRW_REGISTER_TYPE_F,
354 vstride,
355 width,
356 BRW_HORIZONTAL_STRIDE_0,
357 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
358 ADD(dst, src0, negate(src1));
359 }
360
361 /* The negate_value boolean is used to negate the derivative computation for
362 * FBOs, since they place the origin at the upper left instead of the lower
363 * left.
364 */
365 void
366 gen8_fs_generator::generate_ddy(fs_inst *inst,
367 struct brw_reg dst,
368 struct brw_reg src,
369 bool negate_value)
370 {
371 unsigned hstride;
372 unsigned src0_swizzle;
373 unsigned src1_swizzle;
374 unsigned src1_subnr;
375
376 if (key->high_quality_derivatives) {
377 /* Produce accurate derivatives. */
378 hstride = BRW_HORIZONTAL_STRIDE_1;
379 src0_swizzle = BRW_SWIZZLE_XYXY;
380 src1_swizzle = BRW_SWIZZLE_ZWZW;
381 src1_subnr = 0;
382
383 default_state.access_mode = BRW_ALIGN_16;
384 } else {
385 /* Replicate the derivative at the top-left pixel to other pixels. */
386 hstride = BRW_HORIZONTAL_STRIDE_0;
387 src0_swizzle = BRW_SWIZZLE_XYZW;
388 src1_swizzle = BRW_SWIZZLE_XYZW;
389 src1_subnr = 2;
390 }
391
392 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
393 BRW_REGISTER_TYPE_F,
394 BRW_VERTICAL_STRIDE_4,
395 BRW_WIDTH_4,
396 hstride,
397 src0_swizzle, WRITEMASK_XYZW);
398 struct brw_reg src1 = brw_reg(src.file, src.nr, src1_subnr,
399 BRW_REGISTER_TYPE_F,
400 BRW_VERTICAL_STRIDE_4,
401 BRW_WIDTH_4,
402 hstride,
403 src1_swizzle, WRITEMASK_XYZW);
404
405 if (negate_value)
406 ADD(dst, src1, negate(src0));
407 else
408 ADD(dst, src0, negate(src1));
409
410 default_state.access_mode = BRW_ALIGN_1;
411 }
412
413 void
414 gen8_fs_generator::generate_scratch_write(fs_inst *ir, struct brw_reg src)
415 {
416 MOV(retype(brw_message_reg(ir->base_mrf + 1), BRW_REGISTER_TYPE_UD),
417 retype(src, BRW_REGISTER_TYPE_UD));
418
419 struct brw_reg mrf =
420 retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD);
421
422 const int num_regs = dispatch_width / 8;
423
424 uint32_t msg_control;
425 if (num_regs == 1)
426 msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
427 else
428 msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
429
430 /* Set up the message header. This is g0, with g0.2 filled with
431 * the offset. We don't want to leave our offset around in g0 or
432 * it'll screw up texture samples, so set it up inside the message
433 * reg.
434 */
435 unsigned save_exec_size = default_state.exec_size;
436 default_state.exec_size = BRW_EXECUTE_8;
437
438 MOV_RAW(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
439 /* set message header global offset field (reg 0, element 2) */
440 MOV_RAW(get_element_ud(mrf, 2), brw_imm_ud(ir->offset / 16));
441
442 struct brw_reg dst;
443 if (dispatch_width == 16)
444 dst = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
445 else
446 dst = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
447
448 default_state.exec_size = BRW_EXECUTE_16;
449
450 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
451 gen8_set_dst(brw, send, dst);
452 gen8_set_src0(brw, send, mrf);
453 gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE,
454 255, /* binding table index: stateless access */
455 GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE,
456 msg_control,
457 1 + num_regs, /* mlen */
458 0, /* rlen */
459 true, /* header present */
460 false); /* EOT */
461
462 default_state.exec_size = save_exec_size;
463 }
464
465 void
466 gen8_fs_generator::generate_scratch_read(fs_inst *ir, struct brw_reg dst)
467 {
468 struct brw_reg mrf =
469 retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD);
470
471 const int num_regs = dispatch_width / 8;
472
473 uint32_t msg_control;
474 if (num_regs == 1)
475 msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
476 else
477 msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
478
479 unsigned save_exec_size = default_state.exec_size;
480 default_state.exec_size = BRW_EXECUTE_8;
481
482 MOV_RAW(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
483 /* set message header global offset field (reg 0, element 2) */
484 MOV_RAW(get_element_ud(mrf, 2), brw_imm_ud(ir->offset / 16));
485
486 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
487 gen8_set_dst(brw, send, retype(dst, BRW_REGISTER_TYPE_UW));
488 gen8_set_src0(brw, send, mrf);
489 gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE,
490 255, /* binding table index: stateless access */
491 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
492 msg_control,
493 1, /* mlen */
494 num_regs, /* rlen */
495 true, /* header present */
496 false); /* EOT */
497
498 default_state.exec_size = save_exec_size;
499 }
500
501 void
502 gen8_fs_generator::generate_scratch_read_gen7(fs_inst *ir, struct brw_reg dst)
503 {
504 unsigned save_exec_size = default_state.exec_size;
505 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
506
507 int num_regs = dispatch_width / 8;
508
509 /* According to the docs, offset is "A 12-bit HWord offset into the memory
510 * Immediate Memory buffer as specified by binding table 0xFF." An HWORD
511 * is 32 bytes, which happens to be the size of a register.
512 */
513 int offset = ir->offset / REG_SIZE;
514
515 /* The HW requires that the header is present; this is to get the g0.5
516 * scratch offset.
517 */
518 gen8_set_src0(brw, send, brw_vec8_grf(0, 0));
519 gen8_set_dst(brw, send, retype(dst, BRW_REGISTER_TYPE_UW));
520 gen8_set_dp_scratch_message(brw, send,
521 false, /* scratch read */
522 false, /* OWords */
523 false, /* invalidate after read */
524 num_regs,
525 offset,
526 1, /* mlen - just g0 */
527 num_regs, /* rlen */
528 true, /* header present */
529 false); /* EOT */
530
531 default_state.exec_size = save_exec_size;
532 }
533
534 void
535 gen8_fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
536 struct brw_reg dst,
537 struct brw_reg index,
538 struct brw_reg offset)
539 {
540 assert(inst->mlen == 0);
541
542 assert(index.file == BRW_IMMEDIATE_VALUE &&
543 index.type == BRW_REGISTER_TYPE_UD);
544 uint32_t surf_index = index.dw1.ud;
545
546 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
547 /* Reference only the dword we need lest we anger validate_reg() with
548 * reg.width > reg.execszie.
549 */
550 offset = brw_vec1_grf(offset.nr, 0);
551
552 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
553 gen8_set_mask_control(send, BRW_MASK_DISABLE);
554
555 /* We use the SIMD4x2 mode because we want to end up with 4 constants in
556 * the destination loaded consecutively from the same offset (which appears
557 * in the first component, and the rest are ignored).
558 */
559 dst.width = BRW_WIDTH_4;
560 gen8_set_dst(brw, send, dst);
561 gen8_set_src0(brw, send, offset);
562 gen8_set_sampler_message(brw, send,
563 surf_index,
564 0, /* The LD message ignores the sampler unit. */
565 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
566 1, /* rlen */
567 1, /* mlen */
568 false, /* no header */
569 BRW_SAMPLER_SIMD_MODE_SIMD4X2);
570
571 brw_mark_surface_used(&prog_data->base, surf_index);
572 }
573
574 void
575 gen8_fs_generator::generate_varying_pull_constant_load(fs_inst *ir,
576 struct brw_reg dst,
577 struct brw_reg index,
578 struct brw_reg offset)
579 {
580 /* Varying-offset pull constant loads are treated as a normal expression on
581 * gen7, so the fact that it's a send message is hidden at the IR level.
582 */
583 assert(!ir->header_present);
584 assert(!ir->mlen);
585
586 assert(index.file == BRW_IMMEDIATE_VALUE &&
587 index.type == BRW_REGISTER_TYPE_UD);
588 uint32_t surf_index = index.dw1.ud;
589
590 uint32_t simd_mode, rlen, mlen;
591 if (dispatch_width == 16) {
592 mlen = 2;
593 rlen = 8;
594 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
595 } else {
596 mlen = 1;
597 rlen = 4;
598 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
599 }
600
601 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
602 gen8_set_dst(brw, send, dst);
603 gen8_set_src0(brw, send, offset);
604 gen8_set_sampler_message(brw, send,
605 surf_index,
606 0, /* The LD message ignore the sampler unit. */
607 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
608 rlen, /* rlen */
609 mlen, /* mlen */
610 false, /* no header */
611 simd_mode);
612
613 brw_mark_surface_used(&prog_data->base, surf_index);
614 }
615
616 /**
617 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
618 * into the flags register (f0.0).
619 */
620 void
621 gen8_fs_generator::generate_mov_dispatch_to_flags(fs_inst *ir)
622 {
623 struct brw_reg flags = brw_flag_reg(0, ir->flag_subreg);
624 struct brw_reg dispatch_mask =
625 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
626
627 gen8_instruction *mov = MOV(flags, dispatch_mask);
628 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
629 }
630
631 void
632 gen8_fs_generator::generate_discard_jump(fs_inst *ir)
633 {
634 /* This HALT will be patched up at FB write time to point UIP at the end of
635 * the program, and at brw_uip_jip() JIP will be set to the end of the
636 * current block (or the program).
637 */
638 discard_halt_patches.push_tail(new(mem_ctx) ip_record(nr_inst));
639
640 HALT();
641 }
642
643 bool
644 gen8_fs_generator::patch_discard_jumps_to_fb_writes()
645 {
646 if (discard_halt_patches.is_empty())
647 return false;
648
649 /* There is a somewhat strange undocumented requirement of using
650 * HALT, according to the simulator. If some channel has HALTed to
651 * a particular UIP, then by the end of the program, every channel
652 * must have HALTed to that UIP. Furthermore, the tracking is a
653 * stack, so you can't do the final halt of a UIP after starting
654 * halting to a new UIP.
655 *
656 * Symptoms of not emitting this instruction on actual hardware
657 * included GPU hangs and sparkly rendering on the piglit discard
658 * tests.
659 */
660 gen8_instruction *last_halt = HALT();
661 gen8_set_uip(last_halt, 16);
662 gen8_set_jip(last_halt, 16);
663
664 int ip = nr_inst;
665
666 foreach_list(node, &discard_halt_patches) {
667 ip_record *patch_ip = (ip_record *) node;
668 gen8_instruction *patch = &store[patch_ip->ip];
669 assert(gen8_opcode(patch) == BRW_OPCODE_HALT);
670
671 /* HALT takes an instruction distance from the pre-incremented IP. */
672 gen8_set_uip(patch, (ip - patch_ip->ip) * 16);
673 }
674
675 this->discard_halt_patches.make_empty();
676 return true;
677 }
678
679 /**
680 * Sets the first dword of a vgrf for simd4x2 uniform pull constant
681 * sampler LD messages.
682 *
683 * We don't want to bake it into the send message's code generation because
684 * that means we don't get a chance to schedule the instruction.
685 */
686 void
687 gen8_fs_generator::generate_set_simd4x2_offset(fs_inst *ir,
688 struct brw_reg dst,
689 struct brw_reg value)
690 {
691 assert(value.file == BRW_IMMEDIATE_VALUE);
692 MOV_RAW(retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
693 }
694
695 /**
696 * Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
697 * (when mask is passed as a uniform) of register mask before moving it
698 * to register dst.
699 */
700 void
701 gen8_fs_generator::generate_set_omask(fs_inst *inst,
702 struct brw_reg dst,
703 struct brw_reg mask)
704 {
705 assert(dst.type == BRW_REGISTER_TYPE_UW);
706
707 if (dispatch_width == 16)
708 dst = vec16(dst);
709
710 if (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
711 mask.width == BRW_WIDTH_8 &&
712 mask.hstride == BRW_HORIZONTAL_STRIDE_1) {
713 mask = stride(mask, 16, 8, 2);
714 } else {
715 assert(mask.vstride == BRW_VERTICAL_STRIDE_0 &&
716 mask.width == BRW_WIDTH_1 &&
717 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
718 }
719
720 unsigned save_exec_size = default_state.exec_size;
721 default_state.exec_size = BRW_EXECUTE_8;
722
723 gen8_instruction *mov = MOV(dst, retype(mask, dst.type));
724 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
725
726 default_state.exec_size = save_exec_size;
727 }
728
729 /**
730 * Do a special ADD with vstride=1, width=4, hstride=0 for src1.
731 */
732 void
733 gen8_fs_generator::generate_set_sample_id(fs_inst *ir,
734 struct brw_reg dst,
735 struct brw_reg src0,
736 struct brw_reg src1)
737 {
738 assert(dst.type == BRW_REGISTER_TYPE_D || dst.type == BRW_REGISTER_TYPE_UD);
739 assert(src0.type == BRW_REGISTER_TYPE_D || src0.type == BRW_REGISTER_TYPE_UD);
740
741 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
742
743 unsigned save_exec_size = default_state.exec_size;
744 default_state.exec_size = BRW_EXECUTE_8;
745
746 gen8_instruction *add = ADD(dst, src0, reg);
747 gen8_set_mask_control(add, BRW_MASK_DISABLE);
748 if (dispatch_width == 16) {
749 add = ADD(offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
750 gen8_set_mask_control(add, BRW_MASK_DISABLE);
751 }
752
753 default_state.exec_size = save_exec_size;
754 }
755
756 /**
757 * Change the register's data type from UD to HF, doubling the strides in order
758 * to compensate for halving the data type width.
759 */
760 static struct brw_reg
761 ud_reg_to_hf(struct brw_reg r)
762 {
763 assert(r.type == BRW_REGISTER_TYPE_UD);
764 r.type = BRW_REGISTER_TYPE_HF;
765
766 /* The BRW_*_STRIDE enums are defined so that incrementing the field
767 * doubles the real stride.
768 */
769 if (r.hstride != 0)
770 ++r.hstride;
771 if (r.vstride != 0)
772 ++r.vstride;
773
774 return r;
775 }
776
777 void
778 gen8_fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
779 struct brw_reg dst,
780 struct brw_reg x,
781 struct brw_reg y)
782 {
783 assert(dst.type == BRW_REGISTER_TYPE_UD);
784 assert(x.type == BRW_REGISTER_TYPE_F);
785 assert(y.type == BRW_REGISTER_TYPE_F);
786
787 struct brw_reg dst_hf = ud_reg_to_hf(dst);
788
789 /* Give each 32-bit channel of dst the form below , where "." means
790 * unchanged.
791 * 0x....hhhh
792 */
793 MOV(dst_hf, y);
794
795 /* Now the form:
796 * 0xhhhh0000
797 */
798 SHL(dst, dst, brw_imm_ud(16u));
799
800 /* And, finally the form of packHalf2x16's output:
801 * 0xhhhhllll
802 */
803 MOV(dst_hf, x);
804 }
805
806 void
807 gen8_fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
808 struct brw_reg dst,
809 struct brw_reg src)
810 {
811 assert(dst.type == BRW_REGISTER_TYPE_F);
812 assert(src.type == BRW_REGISTER_TYPE_UD);
813
814 struct brw_reg src_hf = ud_reg_to_hf(src);
815
816 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
817 * For the Y case, we wish to access only the upper word; therefore
818 * a 16-bit subregister offset is needed.
819 */
820 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
821 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
822 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
823 src_hf.subnr += 2;
824
825 MOV(dst, src_hf);
826 }
827
828 void
829 gen8_fs_generator::generate_untyped_atomic(fs_inst *ir,
830 struct brw_reg dst,
831 struct brw_reg atomic_op,
832 struct brw_reg surf_index)
833 {
834 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
835 atomic_op.type == BRW_REGISTER_TYPE_UD &&
836 surf_index.file == BRW_IMMEDIATE_VALUE &&
837 surf_index.type == BRW_REGISTER_TYPE_UD);
838 assert((atomic_op.dw1.ud & ~0xf) == 0);
839
840 unsigned msg_control =
841 atomic_op.dw1.ud | /* Atomic Operation Type: BRW_AOP_* */
842 ((dispatch_width == 16 ? 0 : 1) << 4) | /* SIMD Mode */
843 (1 << 5); /* Return data expected */
844
845 gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
846 gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
847 gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
848 gen8_set_dp_message(brw, inst, HSW_SFID_DATAPORT_DATA_CACHE_1,
849 surf_index.dw1.ud,
850 HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP,
851 msg_control,
852 ir->mlen,
853 dispatch_width / 8,
854 ir->header_present,
855 false);
856
857 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
858 }
859
860 void
861 gen8_fs_generator::generate_untyped_surface_read(fs_inst *ir,
862 struct brw_reg dst,
863 struct brw_reg surf_index)
864 {
865 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
866 surf_index.type == BRW_REGISTER_TYPE_UD);
867
868 unsigned msg_control = 0xe | /* Enable only the R channel */
869 ((dispatch_width == 16 ? 1 : 2) << 4); /* SIMD Mode */
870
871 gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
872 gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
873 gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
874 gen8_set_dp_message(brw, inst, HSW_SFID_DATAPORT_DATA_CACHE_1,
875 surf_index.dw1.ud,
876 HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ,
877 msg_control,
878 ir->mlen,
879 dispatch_width / 8,
880 ir->header_present,
881 false);
882
883 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
884 }
885
886 void
887 gen8_fs_generator::generate_code(exec_list *instructions,
888 struct annotation_info *annotation)
889 {
890 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
891 if (prog) {
892 fprintf(stderr,
893 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
894 shader_prog->Label ? shader_prog->Label : "unnamed",
895 shader_prog->Name, dispatch_width);
896 } else if (fp) {
897 fprintf(stderr,
898 "Native code for fragment program %d (SIMD%d dispatch):\n",
899 prog->Id, dispatch_width);
900 } else {
901 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
902 dispatch_width);
903 }
904 }
905
906 cfg_t *cfg = NULL;
907 if (unlikely(INTEL_DEBUG & DEBUG_WM))
908 cfg = new(mem_ctx) cfg_t(instructions);
909
910 foreach_list(node, instructions) {
911 fs_inst *ir = (fs_inst *) node;
912 struct brw_reg src[3], dst;
913
914 if (unlikely(INTEL_DEBUG & DEBUG_WM))
915 annotate(brw, annotation, cfg, ir, next_inst_offset);
916
917 for (unsigned int i = 0; i < 3; i++) {
918 src[i] = brw_reg_from_fs_reg(&ir->src[i]);
919
920 /* The accumulator result appears to get used for the
921 * conditional modifier generation. When negating a UD
922 * value, there is a 33rd bit generated for the sign in the
923 * accumulator value, so now you can't check, for example,
924 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
925 */
926 assert(!ir->conditional_mod ||
927 ir->src[i].type != BRW_REGISTER_TYPE_UD ||
928 !ir->src[i].negate);
929 }
930 dst = brw_reg_from_fs_reg(&ir->dst);
931
932 default_state.conditional_mod = ir->conditional_mod;
933 default_state.predicate = ir->predicate;
934 default_state.predicate_inverse = ir->predicate_inverse;
935 default_state.saturate = ir->saturate;
936 default_state.mask_control = ir->force_writemask_all;
937 default_state.flag_subreg_nr = ir->flag_subreg;
938
939 if (dispatch_width == 16 && !ir->force_uncompressed)
940 default_state.exec_size = BRW_EXECUTE_16;
941 else
942 default_state.exec_size = BRW_EXECUTE_8;
943
944 if (ir->force_uncompressed || dispatch_width == 8)
945 default_state.qtr_control = GEN6_COMPRESSION_1Q;
946 else if (ir->force_sechalf)
947 default_state.qtr_control = GEN6_COMPRESSION_2Q;
948 else
949 default_state.qtr_control = GEN6_COMPRESSION_1H;
950
951 switch (ir->opcode) {
952 case BRW_OPCODE_MOV:
953 MOV(dst, src[0]);
954 break;
955 case BRW_OPCODE_ADD:
956 ADD(dst, src[0], src[1]);
957 break;
958 case BRW_OPCODE_MUL:
959 MUL(dst, src[0], src[1]);
960 break;
961 case BRW_OPCODE_MACH:
962 MACH(dst, src[0], src[1]);
963 break;
964
965 case BRW_OPCODE_MAD:
966 default_state.access_mode = BRW_ALIGN_16;
967 MAD(dst, src[0], src[1], src[2]);
968 default_state.access_mode = BRW_ALIGN_1;
969 break;
970
971 case BRW_OPCODE_LRP:
972 default_state.access_mode = BRW_ALIGN_16;
973 LRP(dst, src[0], src[1], src[2]);
974 default_state.access_mode = BRW_ALIGN_1;
975 break;
976
977
978 case BRW_OPCODE_FRC:
979 FRC(dst, src[0]);
980 break;
981 case BRW_OPCODE_RNDD:
982 RNDD(dst, src[0]);
983 break;
984 case BRW_OPCODE_RNDE:
985 RNDE(dst, src[0]);
986 break;
987 case BRW_OPCODE_RNDZ:
988 RNDZ(dst, src[0]);
989 break;
990
991 case BRW_OPCODE_AND:
992 AND(dst, src[0], src[1]);
993 break;
994 case BRW_OPCODE_OR:
995 OR(dst, src[0], src[1]);
996 break;
997 case BRW_OPCODE_XOR:
998 XOR(dst, src[0], src[1]);
999 break;
1000 case BRW_OPCODE_NOT:
1001 NOT(dst, src[0]);
1002 break;
1003 case BRW_OPCODE_ASR:
1004 ASR(dst, src[0], src[1]);
1005 break;
1006 case BRW_OPCODE_SHR:
1007 SHR(dst, src[0], src[1]);
1008 break;
1009 case BRW_OPCODE_SHL:
1010 SHL(dst, src[0], src[1]);
1011 break;
1012
1013 case BRW_OPCODE_F32TO16:
1014 MOV(retype(dst, BRW_REGISTER_TYPE_HF), src[0]);
1015 break;
1016 case BRW_OPCODE_F16TO32:
1017 MOV(dst, retype(src[0], BRW_REGISTER_TYPE_HF));
1018 break;
1019
1020 case BRW_OPCODE_CMP:
1021 CMP(dst, ir->conditional_mod, src[0], src[1]);
1022 break;
1023 case BRW_OPCODE_SEL:
1024 SEL(dst, src[0], src[1]);
1025 break;
1026
1027 case BRW_OPCODE_BFREV:
1028 /* BFREV only supports UD type for src and dst. */
1029 BFREV(retype(dst, BRW_REGISTER_TYPE_UD),
1030 retype(src[0], BRW_REGISTER_TYPE_UD));
1031 break;
1032
1033 case BRW_OPCODE_FBH:
1034 /* FBH only supports UD type for dst. */
1035 FBH(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1036 break;
1037
1038 case BRW_OPCODE_FBL:
1039 /* FBL only supports UD type for dst. */
1040 FBL(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1041 break;
1042
1043 case BRW_OPCODE_CBIT:
1044 /* CBIT only supports UD type for dst. */
1045 CBIT(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1046 break;
1047
1048 case BRW_OPCODE_ADDC:
1049 ADDC(dst, src[0], src[1]);
1050 break;
1051
1052 case BRW_OPCODE_SUBB:
1053 SUBB(dst, src[0], src[1]);
1054 break;
1055
1056 case BRW_OPCODE_BFE:
1057 default_state.access_mode = BRW_ALIGN_16;
1058 BFE(dst, src[0], src[1], src[2]);
1059 default_state.access_mode = BRW_ALIGN_1;
1060 break;
1061
1062 case BRW_OPCODE_BFI1:
1063 BFI1(dst, src[0], src[1]);
1064 break;
1065
1066 case BRW_OPCODE_BFI2:
1067 default_state.access_mode = BRW_ALIGN_16;
1068 BFI2(dst, src[0], src[1], src[2]);
1069 default_state.access_mode = BRW_ALIGN_1;
1070 break;
1071
1072 case BRW_OPCODE_IF:
1073 IF(BRW_PREDICATE_NORMAL);
1074 break;
1075
1076 case BRW_OPCODE_ELSE:
1077 ELSE();
1078 break;
1079
1080 case BRW_OPCODE_ENDIF:
1081 ENDIF();
1082 break;
1083
1084 case BRW_OPCODE_DO:
1085 DO();
1086 break;
1087
1088 case BRW_OPCODE_BREAK:
1089 BREAK();
1090 break;
1091
1092 case BRW_OPCODE_CONTINUE:
1093 CONTINUE();
1094 break;
1095
1096 case BRW_OPCODE_WHILE:
1097 WHILE();
1098 break;
1099
1100 case SHADER_OPCODE_RCP:
1101 MATH(BRW_MATH_FUNCTION_INV, dst, src[0]);
1102 break;
1103
1104 case SHADER_OPCODE_RSQ:
1105 MATH(BRW_MATH_FUNCTION_RSQ, dst, src[0]);
1106 break;
1107
1108 case SHADER_OPCODE_SQRT:
1109 MATH(BRW_MATH_FUNCTION_SQRT, dst, src[0]);
1110 break;
1111
1112 case SHADER_OPCODE_EXP2:
1113 MATH(BRW_MATH_FUNCTION_EXP, dst, src[0]);
1114 break;
1115
1116 case SHADER_OPCODE_LOG2:
1117 MATH(BRW_MATH_FUNCTION_LOG, dst, src[0]);
1118 break;
1119
1120 case SHADER_OPCODE_SIN:
1121 MATH(BRW_MATH_FUNCTION_SIN, dst, src[0]);
1122 break;
1123
1124 case SHADER_OPCODE_COS:
1125 MATH(BRW_MATH_FUNCTION_COS, dst, src[0]);
1126 break;
1127
1128 case SHADER_OPCODE_INT_QUOTIENT:
1129 MATH(BRW_MATH_FUNCTION_INT_DIV_QUOTIENT, dst, src[0], src[1]);
1130 break;
1131
1132 case SHADER_OPCODE_INT_REMAINDER:
1133 MATH(BRW_MATH_FUNCTION_INT_DIV_REMAINDER, dst, src[0], src[1]);
1134 break;
1135
1136 case SHADER_OPCODE_POW:
1137 MATH(BRW_MATH_FUNCTION_POW, dst, src[0], src[1]);
1138 break;
1139
1140 case FS_OPCODE_PIXEL_X:
1141 case FS_OPCODE_PIXEL_Y:
1142 assert(!"FS_OPCODE_PIXEL_X and FS_OPCODE_PIXEL_Y are only for Gen4-5.");
1143 break;
1144
1145 case FS_OPCODE_CINTERP:
1146 MOV(dst, src[0]);
1147 break;
1148 case FS_OPCODE_LINTERP:
1149 generate_linterp(ir, dst, src);
1150 break;
1151 case SHADER_OPCODE_TEX:
1152 case FS_OPCODE_TXB:
1153 case SHADER_OPCODE_TXD:
1154 case SHADER_OPCODE_TXF:
1155 case SHADER_OPCODE_TXF_CMS:
1156 case SHADER_OPCODE_TXF_UMS:
1157 case SHADER_OPCODE_TXF_MCS:
1158 case SHADER_OPCODE_TXL:
1159 case SHADER_OPCODE_TXS:
1160 case SHADER_OPCODE_LOD:
1161 case SHADER_OPCODE_TG4:
1162 case SHADER_OPCODE_TG4_OFFSET:
1163 generate_tex(ir, dst, src[0]);
1164 break;
1165
1166 case FS_OPCODE_DDX:
1167 generate_ddx(ir, dst, src[0]);
1168 break;
1169 case FS_OPCODE_DDY:
1170 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1171 * guarantee that key->render_to_fbo is set).
1172 */
1173 assert(fp->UsesDFdy);
1174 generate_ddy(ir, dst, src[0], key->render_to_fbo);
1175 break;
1176
1177 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1178 generate_scratch_write(ir, src[0]);
1179 break;
1180
1181 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1182 generate_scratch_read(ir, dst);
1183 break;
1184
1185 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1186 generate_scratch_read_gen7(ir, dst);
1187 break;
1188
1189 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1190 generate_uniform_pull_constant_load(ir, dst, src[0], src[1]);
1191 break;
1192
1193 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1194 generate_varying_pull_constant_load(ir, dst, src[0], src[1]);
1195 break;
1196
1197 case FS_OPCODE_FB_WRITE:
1198 generate_fb_write(ir);
1199 break;
1200
1201 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1202 generate_mov_dispatch_to_flags(ir);
1203 break;
1204
1205 case FS_OPCODE_DISCARD_JUMP:
1206 generate_discard_jump(ir);
1207 break;
1208
1209 case SHADER_OPCODE_SHADER_TIME_ADD:
1210 assert(!"XXX: Missing Gen8 scalar support for INTEL_DEBUG=shader_time");
1211 break;
1212
1213 case SHADER_OPCODE_UNTYPED_ATOMIC:
1214 generate_untyped_atomic(ir, dst, src[0], src[1]);
1215 break;
1216
1217 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1218 generate_untyped_surface_read(ir, dst, src[0]);
1219 break;
1220
1221 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1222 generate_set_simd4x2_offset(ir, dst, src[0]);
1223 break;
1224
1225 case FS_OPCODE_SET_OMASK:
1226 generate_set_omask(ir, dst, src[0]);
1227 break;
1228
1229 case FS_OPCODE_SET_SAMPLE_ID:
1230 generate_set_sample_id(ir, dst, src[0], src[1]);
1231 break;
1232
1233 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1234 generate_pack_half_2x16_split(ir, dst, src[0], src[1]);
1235 break;
1236
1237 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1238 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1239 generate_unpack_half_2x16_split(ir, dst, src[0]);
1240 break;
1241
1242 case FS_OPCODE_PLACEHOLDER_HALT:
1243 /* This is the place where the final HALT needs to be inserted if
1244 * we've emitted any discards. If not, this will emit no code.
1245 */
1246 patch_discard_jumps_to_fb_writes();
1247 break;
1248
1249 default:
1250 if (ir->opcode < int(ARRAY_SIZE(opcode_descs))) {
1251 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1252 opcode_descs[ir->opcode].name);
1253 } else {
1254 _mesa_problem(ctx, "Unsupported opcode %d in FS", ir->opcode);
1255 }
1256 abort();
1257 }
1258 }
1259
1260 patch_jump_targets();
1261 annotation_finalize(annotation, next_inst_offset);
1262 }
1263
1264 const unsigned *
1265 gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
1266 exec_list *simd16_instructions,
1267 unsigned *assembly_size)
1268 {
1269 assert(simd8_instructions || simd16_instructions);
1270
1271 if (simd8_instructions) {
1272 struct annotation_info annotation;
1273 memset(&annotation, 0, sizeof(annotation));
1274
1275 dispatch_width = 8;
1276 generate_code(simd8_instructions, &annotation);
1277
1278 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1279 dump_assembly(store, annotation.ann_count, annotation.ann, brw, prog,
1280 gen8_disassemble);
1281 ralloc_free(annotation.ann);
1282 }
1283 }
1284
1285 if (simd16_instructions) {
1286 /* Align to a 64-byte boundary. */
1287 while (next_inst_offset % 64)
1288 NOP();
1289
1290 /* Save off the start of this SIMD16 program */
1291 prog_data->prog_offset_16 = next_inst_offset;
1292
1293 struct annotation_info annotation;
1294 memset(&annotation, 0, sizeof(annotation));
1295
1296 dispatch_width = 16;
1297 generate_code(simd16_instructions, &annotation);
1298
1299 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1300 dump_assembly(store, annotation.ann_count, annotation.ann,
1301 brw, prog, gen8_disassemble);
1302 ralloc_free(annotation.ann);
1303 }
1304 }
1305
1306 *assembly_size = next_inst_offset;
1307 return (const unsigned *) store;
1308 }