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i965/fs: Port untyped surface read support to Broadwell.
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_fs_generator.cpp
1 /*
2 * Copyright © 2010, 2011, 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file gen8_fs_generate.cpp
25 *
26 * Code generation for Gen8+ hardware.
27 */
28
29 extern "C" {
30 #include "main/macros.h"
31 #include "brw_context.h"
32 } /* extern "C" */
33
34 #include "brw_fs.h"
35 #include "brw_cfg.h"
36 #include "glsl/ir_print_visitor.h"
37
38 gen8_fs_generator::gen8_fs_generator(struct brw_context *brw,
39 struct brw_wm_compile *c,
40 struct gl_shader_program *shader_prog,
41 struct gl_fragment_program *fp,
42 bool dual_source_output)
43 : gen8_generator(brw, shader_prog, fp ? &fp->Base : NULL, c), c(c), fp(fp),
44 dual_source_output(dual_source_output)
45 {
46 }
47
48 gen8_fs_generator::~gen8_fs_generator()
49 {
50 }
51
52 void
53 gen8_fs_generator::generate_fb_write(fs_inst *ir)
54 {
55 /* Disable the discard condition while setting up the header. */
56 default_state.predicate = BRW_PREDICATE_NONE;
57 default_state.predicate_inverse = false;
58 default_state.flag_subreg_nr = 0;
59
60 if (ir->header_present) {
61 /* The GPU will use the predicate on SENDC, unless the header is present.
62 */
63 if (fp && fp->UsesKill) {
64 gen8_instruction *mov =
65 MOV(retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW),
66 brw_flag_reg(0, 1));
67 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
68 }
69
70 gen8_instruction *mov =
71 MOV_RAW(brw_message_reg(ir->base_mrf), brw_vec8_grf(0, 0));
72 gen8_set_exec_size(mov, BRW_EXECUTE_16);
73
74 if (ir->target > 0 && c->key.replicate_alpha) {
75 /* Set "Source0 Alpha Present to RenderTarget" bit in the header. */
76 OR(vec1(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD)),
77 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
78 brw_imm_ud(1 << 11));
79 }
80
81 if (ir->target > 0) {
82 /* Set the render target index for choosing BLEND_STATE. */
83 MOV(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2),
84 BRW_REGISTER_TYPE_UD),
85 brw_imm_ud(ir->target));
86 }
87 }
88
89 /* Set the predicate back to get the conditional write if necessary for
90 * discards.
91 */
92 default_state.predicate = ir->predicate;
93 default_state.predicate_inverse = ir->predicate_inverse;
94 default_state.flag_subreg_nr = ir->flag_subreg;
95
96 gen8_instruction *inst = next_inst(BRW_OPCODE_SENDC);
97 gen8_set_dst(brw, inst, retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW));
98 gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
99
100 /* Set up the "Message Specific Control" bits for the Data Port Message
101 * Descriptor. These are documented in the "Render Target Write" message's
102 * "Message Descriptor" documentation (vol5c.2).
103 */
104 uint32_t msg_type;
105 /* Set the Message Type */
106 if (this->dual_source_output)
107 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
108 else if (dispatch_width == 16)
109 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
110 else
111 msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
112
113 uint32_t msg_control = msg_type;
114
115 /* "Last Render Target Select" must be set on all writes to the last of
116 * the render targets (if using MRT), or always for a single RT scenario.
117 */
118 if ((ir->target == c->key.nr_color_regions - 1) || !c->key.nr_color_regions)
119 msg_control |= (1 << 4); /* Last Render Target Select */
120
121 uint32_t surf_index =
122 c->prog_data.binding_table.render_target_start + ir->target;
123
124 gen8_set_dp_message(brw, inst,
125 GEN6_SFID_DATAPORT_RENDER_CACHE,
126 surf_index,
127 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
128 msg_control,
129 ir->mlen,
130 0,
131 ir->header_present,
132 ir->eot);
133
134 brw_mark_surface_used(&c->prog_data.base, surf_index);
135 }
136
137 void
138 gen8_fs_generator::generate_linterp(fs_inst *inst,
139 struct brw_reg dst,
140 struct brw_reg *src)
141 {
142 struct brw_reg delta_x = src[0];
143 struct brw_reg delta_y = src[1];
144 struct brw_reg interp = src[2];
145
146 (void) delta_y;
147 assert(delta_y.nr == delta_x.nr + 1);
148 PLN(dst, interp, delta_x);
149 }
150
151 void
152 gen8_fs_generator::generate_tex(fs_inst *ir,
153 struct brw_reg dst,
154 struct brw_reg src)
155 {
156 int msg_type = -1;
157 int rlen = 4;
158 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
159
160 assert(src.file == BRW_GENERAL_REGISTER_FILE);
161
162 if (dispatch_width == 16 && !ir->force_uncompressed && !ir->force_sechalf)
163 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
164
165 switch (ir->opcode) {
166 case SHADER_OPCODE_TEX:
167 if (ir->shadow_compare) {
168 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
169 } else {
170 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
171 }
172 break;
173 case FS_OPCODE_TXB:
174 if (ir->shadow_compare) {
175 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
176 } else {
177 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
178 }
179 break;
180 case SHADER_OPCODE_TXL:
181 if (ir->shadow_compare) {
182 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
183 } else {
184 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
185 }
186 break;
187 case SHADER_OPCODE_TXS:
188 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
189 break;
190 case SHADER_OPCODE_TXD:
191 if (ir->shadow_compare) {
192 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
193 } else {
194 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
195 }
196 break;
197 case SHADER_OPCODE_TXF:
198 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
199 break;
200 case SHADER_OPCODE_TXF_CMS:
201 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
202 break;
203 case SHADER_OPCODE_TXF_UMS:
204 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
205 break;
206 case SHADER_OPCODE_TXF_MCS:
207 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
208 break;
209 case SHADER_OPCODE_LOD:
210 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
211 break;
212 case SHADER_OPCODE_TG4:
213 if (ir->shadow_compare) {
214 assert(brw->gen >= 7);
215 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
216 } else {
217 assert(brw->gen >= 6);
218 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
219 }
220 break;
221 case SHADER_OPCODE_TG4_OFFSET:
222 assert(brw->gen >= 7);
223 if (ir->shadow_compare) {
224 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
225 } else {
226 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
227 }
228 break;
229 default:
230 assert(!"not reached");
231 break;
232 }
233 assert(msg_type != -1);
234
235 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
236 rlen = 8;
237 dst = vec16(dst);
238 }
239
240 if (ir->header_present) {
241 /* The send-from-GRF for SIMD16 texturing with a header has an extra
242 * hardware register allocated to it, which we need to skip over (since
243 * our coordinates in the payload are in the even-numbered registers,
244 * and the header comes right before the first one.
245 */
246 if (dispatch_width == 16)
247 src.nr++;
248
249 unsigned save_exec_size = default_state.exec_size;
250 default_state.exec_size = BRW_EXECUTE_8;
251
252 MOV_RAW(src, brw_vec8_grf(0, 0));
253
254 if (ir->texture_offset) {
255 /* Set the texel offset bits. */
256 MOV_RAW(retype(brw_vec1_grf(src.nr, 2), BRW_REGISTER_TYPE_UD),
257 brw_imm_ud(ir->texture_offset));
258 }
259
260 if (ir->sampler >= 16) {
261 /* The "Sampler Index" field can only store values between 0 and 15.
262 * However, we can add an offset to the "Sampler State Pointer"
263 * field, effectively selecting a different set of 16 samplers.
264 *
265 * The "Sampler State Pointer" needs to be aligned to a 32-byte
266 * offset, and each sampler state is only 16-bytes, so we can't
267 * exclusively use the offset - we have to use both.
268 */
269 gen8_instruction *add =
270 ADD(get_element_ud(src, 3),
271 get_element_ud(brw_vec8_grf(0, 0), 3),
272 brw_imm_ud(16 * (ir->sampler / 16) *
273 sizeof(gen7_sampler_state)));
274 gen8_set_mask_control(add, BRW_MASK_DISABLE);
275 }
276
277 default_state.exec_size = save_exec_size;
278 }
279
280 uint32_t surf_index =
281 c->prog_data.base.binding_table.texture_start + ir->sampler;
282
283 gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
284 gen8_set_dst(brw, inst, dst);
285 gen8_set_src0(brw, inst, src);
286 gen8_set_sampler_message(brw, inst,
287 surf_index,
288 ir->sampler % 16,
289 msg_type,
290 rlen,
291 ir->mlen,
292 ir->header_present,
293 simd_mode);
294
295 brw_mark_surface_used(&c->prog_data.base, surf_index);
296 }
297
298
299 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
300 * looking like:
301 *
302 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
303 *
304 * and we're trying to produce:
305 *
306 * DDX DDY
307 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
308 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
309 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
310 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
311 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
312 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
313 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
314 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
315 *
316 * and add another set of two more subspans if in 16-pixel dispatch mode.
317 *
318 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
319 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
320 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
321 * between each other. We could probably do it like ddx and swizzle the right
322 * order later, but bail for now and just produce
323 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
324 */
325 void
326 gen8_fs_generator::generate_ddx(fs_inst *inst,
327 struct brw_reg dst,
328 struct brw_reg src)
329 {
330 unsigned vstride, width;
331
332 if (c->key.high_quality_derivatives) {
333 /* Produce accurate derivatives. */
334 vstride = BRW_VERTICAL_STRIDE_2;
335 width = BRW_WIDTH_2;
336 } else {
337 /* Replicate the derivative at the top-left pixel to other pixels. */
338 vstride = BRW_VERTICAL_STRIDE_4;
339 width = BRW_WIDTH_4;
340 }
341
342 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
343 BRW_REGISTER_TYPE_F,
344 vstride,
345 width,
346 BRW_HORIZONTAL_STRIDE_0,
347 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
348 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
349 BRW_REGISTER_TYPE_F,
350 vstride,
351 width,
352 BRW_HORIZONTAL_STRIDE_0,
353 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
354 ADD(dst, src0, negate(src1));
355 }
356
357 /* The negate_value boolean is used to negate the derivative computation for
358 * FBOs, since they place the origin at the upper left instead of the lower
359 * left.
360 */
361 void
362 gen8_fs_generator::generate_ddy(fs_inst *inst,
363 struct brw_reg dst,
364 struct brw_reg src,
365 bool negate_value)
366 {
367 unsigned hstride;
368 unsigned src0_swizzle;
369 unsigned src1_swizzle;
370 unsigned src1_subnr;
371
372 if (c->key.high_quality_derivatives) {
373 /* Produce accurate derivatives. */
374 hstride = BRW_HORIZONTAL_STRIDE_1;
375 src0_swizzle = BRW_SWIZZLE_XYXY;
376 src1_swizzle = BRW_SWIZZLE_ZWZW;
377 src1_subnr = 0;
378
379 default_state.access_mode = BRW_ALIGN_16;
380 } else {
381 /* Replicate the derivative at the top-left pixel to other pixels. */
382 hstride = BRW_HORIZONTAL_STRIDE_0;
383 src0_swizzle = BRW_SWIZZLE_XYZW;
384 src1_swizzle = BRW_SWIZZLE_XYZW;
385 src1_subnr = 2;
386 }
387
388 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
389 BRW_REGISTER_TYPE_F,
390 BRW_VERTICAL_STRIDE_4,
391 BRW_WIDTH_4,
392 hstride,
393 src0_swizzle, WRITEMASK_XYZW);
394 struct brw_reg src1 = brw_reg(src.file, src.nr, src1_subnr,
395 BRW_REGISTER_TYPE_F,
396 BRW_VERTICAL_STRIDE_4,
397 BRW_WIDTH_4,
398 hstride,
399 src1_swizzle, WRITEMASK_XYZW);
400
401 if (negate_value)
402 ADD(dst, src1, negate(src0));
403 else
404 ADD(dst, src0, negate(src1));
405
406 default_state.access_mode = BRW_ALIGN_1;
407 }
408
409 void
410 gen8_fs_generator::generate_scratch_write(fs_inst *ir, struct brw_reg src)
411 {
412 MOV(retype(brw_message_reg(ir->base_mrf + 1), BRW_REGISTER_TYPE_UD),
413 retype(src, BRW_REGISTER_TYPE_UD));
414
415 struct brw_reg mrf =
416 retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD);
417
418 const int num_regs = dispatch_width / 8;
419
420 uint32_t msg_control;
421 if (num_regs == 1)
422 msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
423 else
424 msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
425
426 /* Set up the message header. This is g0, with g0.2 filled with
427 * the offset. We don't want to leave our offset around in g0 or
428 * it'll screw up texture samples, so set it up inside the message
429 * reg.
430 */
431 unsigned save_exec_size = default_state.exec_size;
432 default_state.exec_size = BRW_EXECUTE_8;
433
434 MOV_RAW(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
435 /* set message header global offset field (reg 0, element 2) */
436 MOV_RAW(get_element_ud(mrf, 2), brw_imm_ud(ir->offset / 16));
437
438 struct brw_reg dst;
439 if (dispatch_width == 16)
440 dst = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
441 else
442 dst = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
443
444 default_state.exec_size = BRW_EXECUTE_16;
445
446 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
447 gen8_set_dst(brw, send, dst);
448 gen8_set_src0(brw, send, mrf);
449 gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE,
450 255, /* binding table index: stateless access */
451 GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE,
452 msg_control,
453 1 + num_regs, /* mlen */
454 0, /* rlen */
455 true, /* header present */
456 false); /* EOT */
457
458 default_state.exec_size = save_exec_size;
459 }
460
461 void
462 gen8_fs_generator::generate_scratch_read(fs_inst *ir, struct brw_reg dst)
463 {
464 struct brw_reg mrf =
465 retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD);
466
467 const int num_regs = dispatch_width / 8;
468
469 uint32_t msg_control;
470 if (num_regs == 1)
471 msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
472 else
473 msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
474
475 unsigned save_exec_size = default_state.exec_size;
476 default_state.exec_size = BRW_EXECUTE_8;
477
478 MOV_RAW(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
479 /* set message header global offset field (reg 0, element 2) */
480 MOV_RAW(get_element_ud(mrf, 2), brw_imm_ud(ir->offset / 16));
481
482 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
483 gen8_set_dst(brw, send, retype(dst, BRW_REGISTER_TYPE_UW));
484 gen8_set_src0(brw, send, mrf);
485 gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE,
486 255, /* binding table index: stateless access */
487 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
488 msg_control,
489 1, /* mlen */
490 num_regs, /* rlen */
491 true, /* header present */
492 false); /* EOT */
493
494 default_state.exec_size = save_exec_size;
495 }
496
497 void
498 gen8_fs_generator::generate_scratch_read_gen7(fs_inst *ir, struct brw_reg dst)
499 {
500 unsigned save_exec_size = default_state.exec_size;
501 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
502
503 int num_regs = dispatch_width / 8;
504
505 /* According to the docs, offset is "A 12-bit HWord offset into the memory
506 * Immediate Memory buffer as specified by binding table 0xFF." An HWORD
507 * is 32 bytes, which happens to be the size of a register.
508 */
509 int offset = ir->offset / REG_SIZE;
510
511 /* The HW requires that the header is present; this is to get the g0.5
512 * scratch offset.
513 */
514 gen8_set_src0(brw, send, brw_vec8_grf(0, 0));
515 gen8_set_dst(brw, send, retype(dst, BRW_REGISTER_TYPE_UW));
516 gen8_set_dp_scratch_message(brw, send,
517 false, /* scratch read */
518 false, /* OWords */
519 false, /* invalidate after read */
520 num_regs,
521 offset,
522 1, /* mlen - just g0 */
523 num_regs, /* rlen */
524 true, /* header present */
525 false); /* EOT */
526
527 default_state.exec_size = save_exec_size;
528 }
529
530 void
531 gen8_fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
532 struct brw_reg dst,
533 struct brw_reg index,
534 struct brw_reg offset)
535 {
536 assert(inst->mlen == 0);
537
538 assert(index.file == BRW_IMMEDIATE_VALUE &&
539 index.type == BRW_REGISTER_TYPE_UD);
540 uint32_t surf_index = index.dw1.ud;
541
542 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
543 /* Reference only the dword we need lest we anger validate_reg() with
544 * reg.width > reg.execszie.
545 */
546 offset = brw_vec1_grf(offset.nr, 0);
547
548 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
549 gen8_set_mask_control(send, BRW_MASK_DISABLE);
550
551 /* We use the SIMD4x2 mode because we want to end up with 4 constants in
552 * the destination loaded consecutively from the same offset (which appears
553 * in the first component, and the rest are ignored).
554 */
555 dst.width = BRW_WIDTH_4;
556 gen8_set_dst(brw, send, dst);
557 gen8_set_src0(brw, send, offset);
558 gen8_set_sampler_message(brw, send,
559 surf_index,
560 0, /* The LD message ignores the sampler unit. */
561 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
562 1, /* rlen */
563 1, /* mlen */
564 false, /* no header */
565 BRW_SAMPLER_SIMD_MODE_SIMD4X2);
566
567 brw_mark_surface_used(&c->prog_data.base, surf_index);
568 }
569
570 void
571 gen8_fs_generator::generate_varying_pull_constant_load(fs_inst *ir,
572 struct brw_reg dst,
573 struct brw_reg index,
574 struct brw_reg offset)
575 {
576 /* Varying-offset pull constant loads are treated as a normal expression on
577 * gen7, so the fact that it's a send message is hidden at the IR level.
578 */
579 assert(!ir->header_present);
580 assert(!ir->mlen);
581
582 assert(index.file == BRW_IMMEDIATE_VALUE &&
583 index.type == BRW_REGISTER_TYPE_UD);
584 uint32_t surf_index = index.dw1.ud;
585
586 uint32_t simd_mode, rlen, mlen;
587 if (dispatch_width == 16) {
588 mlen = 2;
589 rlen = 8;
590 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
591 } else {
592 mlen = 1;
593 rlen = 4;
594 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
595 }
596
597 gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
598 gen8_set_dst(brw, send, dst);
599 gen8_set_src0(brw, send, offset);
600 gen8_set_sampler_message(brw, send,
601 surf_index,
602 0, /* The LD message ignore the sampler unit. */
603 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
604 rlen, /* rlen */
605 mlen, /* mlen */
606 false, /* no header */
607 simd_mode);
608
609 brw_mark_surface_used(&c->prog_data.base, surf_index);
610 }
611
612 /**
613 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
614 * into the flags register (f0.0).
615 */
616 void
617 gen8_fs_generator::generate_mov_dispatch_to_flags(fs_inst *ir)
618 {
619 struct brw_reg flags = brw_flag_reg(0, ir->flag_subreg);
620 struct brw_reg dispatch_mask =
621 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
622
623 gen8_instruction *mov = MOV(flags, dispatch_mask);
624 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
625 }
626
627 void
628 gen8_fs_generator::generate_discard_jump(fs_inst *ir)
629 {
630 /* This HALT will be patched up at FB write time to point UIP at the end of
631 * the program, and at brw_uip_jip() JIP will be set to the end of the
632 * current block (or the program).
633 */
634 discard_halt_patches.push_tail(new(mem_ctx) ip_record(nr_inst));
635
636 HALT();
637 }
638
639 void
640 gen8_fs_generator::patch_discard_jumps_to_fb_writes()
641 {
642 if (discard_halt_patches.is_empty())
643 return;
644
645 /* There is a somewhat strange undocumented requirement of using
646 * HALT, according to the simulator. If some channel has HALTed to
647 * a particular UIP, then by the end of the program, every channel
648 * must have HALTed to that UIP. Furthermore, the tracking is a
649 * stack, so you can't do the final halt of a UIP after starting
650 * halting to a new UIP.
651 *
652 * Symptoms of not emitting this instruction on actual hardware
653 * included GPU hangs and sparkly rendering on the piglit discard
654 * tests.
655 */
656 gen8_instruction *last_halt = HALT();
657 gen8_set_uip(last_halt, 16);
658 gen8_set_jip(last_halt, 16);
659
660 int ip = nr_inst;
661
662 foreach_list(node, &discard_halt_patches) {
663 ip_record *patch_ip = (ip_record *) node;
664 gen8_instruction *patch = &store[patch_ip->ip];
665 assert(gen8_opcode(patch) == BRW_OPCODE_HALT);
666
667 /* HALT takes an instruction distance from the pre-incremented IP. */
668 gen8_set_uip(patch, (ip - patch_ip->ip) * 16);
669 }
670
671 this->discard_halt_patches.make_empty();
672 }
673
674 /**
675 * Sets the first dword of a vgrf for simd4x2 uniform pull constant
676 * sampler LD messages.
677 *
678 * We don't want to bake it into the send message's code generation because
679 * that means we don't get a chance to schedule the instruction.
680 */
681 void
682 gen8_fs_generator::generate_set_simd4x2_offset(fs_inst *ir,
683 struct brw_reg dst,
684 struct brw_reg value)
685 {
686 assert(value.file == BRW_IMMEDIATE_VALUE);
687 MOV_RAW(retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
688 }
689
690 /**
691 * Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
692 * (when mask is passed as a uniform) of register mask before moving it
693 * to register dst.
694 */
695 void
696 gen8_fs_generator::generate_set_omask(fs_inst *inst,
697 struct brw_reg dst,
698 struct brw_reg mask)
699 {
700 assert(dst.type == BRW_REGISTER_TYPE_UW);
701
702 if (dispatch_width == 16)
703 dst = vec16(dst);
704
705 if (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
706 mask.width == BRW_WIDTH_8 &&
707 mask.hstride == BRW_HORIZONTAL_STRIDE_1) {
708 mask = stride(mask, 16, 8, 2);
709 } else {
710 assert(mask.vstride == BRW_VERTICAL_STRIDE_0 &&
711 mask.width == BRW_WIDTH_1 &&
712 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
713 }
714
715 unsigned save_exec_size = default_state.exec_size;
716 default_state.exec_size = BRW_EXECUTE_8;
717
718 gen8_instruction *mov = MOV(dst, retype(mask, dst.type));
719 gen8_set_mask_control(mov, BRW_MASK_DISABLE);
720
721 default_state.exec_size = save_exec_size;
722 }
723
724 /**
725 * Do a special ADD with vstride=1, width=4, hstride=0 for src1.
726 */
727 void
728 gen8_fs_generator::generate_set_sample_id(fs_inst *ir,
729 struct brw_reg dst,
730 struct brw_reg src0,
731 struct brw_reg src1)
732 {
733 assert(dst.type == BRW_REGISTER_TYPE_D || dst.type == BRW_REGISTER_TYPE_UD);
734 assert(src0.type == BRW_REGISTER_TYPE_D || src0.type == BRW_REGISTER_TYPE_UD);
735
736 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
737
738 unsigned save_exec_size = default_state.exec_size;
739 default_state.exec_size = BRW_EXECUTE_8;
740
741 gen8_instruction *add = ADD(dst, src0, reg);
742 gen8_set_mask_control(add, BRW_MASK_DISABLE);
743 if (dispatch_width == 16) {
744 add = ADD(offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
745 gen8_set_mask_control(add, BRW_MASK_DISABLE);
746 }
747
748 default_state.exec_size = save_exec_size;
749 }
750
751 /**
752 * Change the register's data type from UD to HF, doubling the strides in order
753 * to compensate for halving the data type width.
754 */
755 static struct brw_reg
756 ud_reg_to_hf(struct brw_reg r)
757 {
758 assert(r.type == BRW_REGISTER_TYPE_UD);
759 r.type = BRW_REGISTER_TYPE_HF;
760
761 /* The BRW_*_STRIDE enums are defined so that incrementing the field
762 * doubles the real stride.
763 */
764 if (r.hstride != 0)
765 ++r.hstride;
766 if (r.vstride != 0)
767 ++r.vstride;
768
769 return r;
770 }
771
772 void
773 gen8_fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
774 struct brw_reg dst,
775 struct brw_reg x,
776 struct brw_reg y)
777 {
778 assert(dst.type == BRW_REGISTER_TYPE_UD);
779 assert(x.type == BRW_REGISTER_TYPE_F);
780 assert(y.type == BRW_REGISTER_TYPE_F);
781
782 struct brw_reg dst_hf = ud_reg_to_hf(dst);
783
784 /* Give each 32-bit channel of dst the form below , where "." means
785 * unchanged.
786 * 0x....hhhh
787 */
788 MOV(dst_hf, y);
789
790 /* Now the form:
791 * 0xhhhh0000
792 */
793 SHL(dst, dst, brw_imm_ud(16u));
794
795 /* And, finally the form of packHalf2x16's output:
796 * 0xhhhhllll
797 */
798 MOV(dst_hf, x);
799 }
800
801 void
802 gen8_fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
803 struct brw_reg dst,
804 struct brw_reg src)
805 {
806 assert(dst.type == BRW_REGISTER_TYPE_F);
807 assert(src.type == BRW_REGISTER_TYPE_UD);
808
809 struct brw_reg src_hf = ud_reg_to_hf(src);
810
811 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
812 * For the Y case, we wish to access only the upper word; therefore
813 * a 16-bit subregister offset is needed.
814 */
815 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
816 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
817 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
818 src_hf.subnr += 2;
819
820 MOV(dst, src_hf);
821 }
822
823 void
824 gen8_fs_generator::generate_untyped_surface_read(fs_inst *ir,
825 struct brw_reg dst,
826 struct brw_reg surf_index)
827 {
828 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
829 surf_index.type == BRW_REGISTER_TYPE_UD);
830
831 unsigned msg_control = 0xe | /* Enable only the R channel */
832 ((dispatch_width == 16 ? 1 : 2) << 4); /* SIMD Mode */
833
834 gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
835 gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD));
836 gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
837 gen8_set_dp_message(brw, inst, HSW_SFID_DATAPORT_DATA_CACHE_1,
838 surf_index.dw1.ud,
839 HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ,
840 msg_control,
841 ir->mlen,
842 dispatch_width / 8,
843 ir->header_present,
844 false);
845
846 brw_mark_surface_used(&c->prog_data.base, surf_index.dw1.ud);
847 }
848
849 void
850 gen8_fs_generator::generate_code(exec_list *instructions)
851 {
852 int last_native_inst_offset = next_inst_offset;
853 const char *last_annotation_string = NULL;
854 const void *last_annotation_ir = NULL;
855
856 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
857 if (prog) {
858 fprintf(stderr,
859 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
860 shader_prog->Label ? shader_prog->Label : "unnamed",
861 shader_prog->Name, dispatch_width);
862 } else if (fp) {
863 fprintf(stderr,
864 "Native code for fragment program %d (SIMD%d dispatch):\n",
865 prog->Id, dispatch_width);
866 } else {
867 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
868 dispatch_width);
869 }
870 }
871
872 cfg_t *cfg = NULL;
873 if (unlikely(INTEL_DEBUG & DEBUG_WM))
874 cfg = new(mem_ctx) cfg_t(instructions);
875
876 foreach_list(node, instructions) {
877 fs_inst *ir = (fs_inst *) node;
878 struct brw_reg src[3], dst;
879
880 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
881 foreach_list(node, &cfg->block_list) {
882 bblock_link *link = (bblock_link *)node;
883 bblock_t *block = link->block;
884
885 if (block->start == ir) {
886 fprintf(stderr, " START B%d", block->block_num);
887 foreach_list(predecessor_node, &block->parents) {
888 bblock_link *predecessor_link =
889 (bblock_link *)predecessor_node;
890 bblock_t *predecessor_block = predecessor_link->block;
891 fprintf(stderr, " <-B%d", predecessor_block->block_num);
892 }
893 fprintf(stderr, "\n");
894 }
895 }
896
897 if (last_annotation_ir != ir->ir) {
898 last_annotation_ir = ir->ir;
899 if (last_annotation_ir) {
900 fprintf(stderr, " ");
901 if (prog) {
902 ((ir_instruction *) ir->ir)->fprint(stderr);
903 } else if (prog) {
904 const prog_instruction *fpi;
905 fpi = (const prog_instruction *) ir->ir;
906 fprintf(stderr, "%d: ", (int)(fpi - prog->Instructions));
907 _mesa_fprint_instruction_opt(stderr,
908 fpi,
909 0, PROG_PRINT_DEBUG, NULL);
910 }
911 fprintf(stderr, "\n");
912 }
913 }
914 if (last_annotation_string != ir->annotation) {
915 last_annotation_string = ir->annotation;
916 if (last_annotation_string)
917 fprintf(stderr, " %s\n", last_annotation_string);
918 }
919 }
920
921 for (unsigned int i = 0; i < 3; i++) {
922 src[i] = brw_reg_from_fs_reg(&ir->src[i]);
923
924 /* The accumulator result appears to get used for the
925 * conditional modifier generation. When negating a UD
926 * value, there is a 33rd bit generated for the sign in the
927 * accumulator value, so now you can't check, for example,
928 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
929 */
930 assert(!ir->conditional_mod ||
931 ir->src[i].type != BRW_REGISTER_TYPE_UD ||
932 !ir->src[i].negate);
933 }
934 dst = brw_reg_from_fs_reg(&ir->dst);
935
936 default_state.conditional_mod = ir->conditional_mod;
937 default_state.predicate = ir->predicate;
938 default_state.predicate_inverse = ir->predicate_inverse;
939 default_state.saturate = ir->saturate;
940 default_state.mask_control = ir->force_writemask_all;
941 default_state.flag_subreg_nr = ir->flag_subreg;
942
943 if (dispatch_width == 16 && !ir->force_uncompressed)
944 default_state.exec_size = BRW_EXECUTE_16;
945 else
946 default_state.exec_size = BRW_EXECUTE_8;
947
948 if (ir->force_uncompressed || dispatch_width == 8)
949 default_state.qtr_control = GEN6_COMPRESSION_1Q;
950 else if (ir->force_sechalf)
951 default_state.qtr_control = GEN6_COMPRESSION_2Q;
952 else
953 default_state.qtr_control = GEN6_COMPRESSION_1H;
954
955 switch (ir->opcode) {
956 case BRW_OPCODE_MOV:
957 MOV(dst, src[0]);
958 break;
959 case BRW_OPCODE_ADD:
960 ADD(dst, src[0], src[1]);
961 break;
962 case BRW_OPCODE_MUL:
963 MUL(dst, src[0], src[1]);
964 break;
965 case BRW_OPCODE_MACH:
966 MACH(dst, src[0], src[1]);
967 break;
968
969 case BRW_OPCODE_MAD:
970 default_state.access_mode = BRW_ALIGN_16;
971 MAD(dst, src[0], src[1], src[2]);
972 default_state.access_mode = BRW_ALIGN_1;
973 break;
974
975 case BRW_OPCODE_LRP:
976 default_state.access_mode = BRW_ALIGN_16;
977 LRP(dst, src[0], src[1], src[2]);
978 default_state.access_mode = BRW_ALIGN_1;
979 break;
980
981
982 case BRW_OPCODE_FRC:
983 FRC(dst, src[0]);
984 break;
985 case BRW_OPCODE_RNDD:
986 RNDD(dst, src[0]);
987 break;
988 case BRW_OPCODE_RNDE:
989 RNDE(dst, src[0]);
990 break;
991 case BRW_OPCODE_RNDZ:
992 RNDZ(dst, src[0]);
993 break;
994
995 case BRW_OPCODE_AND:
996 AND(dst, src[0], src[1]);
997 break;
998 case BRW_OPCODE_OR:
999 OR(dst, src[0], src[1]);
1000 break;
1001 case BRW_OPCODE_XOR:
1002 XOR(dst, src[0], src[1]);
1003 break;
1004 case BRW_OPCODE_NOT:
1005 NOT(dst, src[0]);
1006 break;
1007 case BRW_OPCODE_ASR:
1008 ASR(dst, src[0], src[1]);
1009 break;
1010 case BRW_OPCODE_SHR:
1011 SHR(dst, src[0], src[1]);
1012 break;
1013 case BRW_OPCODE_SHL:
1014 SHL(dst, src[0], src[1]);
1015 break;
1016
1017 case BRW_OPCODE_F32TO16:
1018 MOV(retype(dst, BRW_REGISTER_TYPE_HF), src[0]);
1019 break;
1020 case BRW_OPCODE_F16TO32:
1021 MOV(dst, retype(src[0], BRW_REGISTER_TYPE_HF));
1022 break;
1023
1024 case BRW_OPCODE_CMP:
1025 CMP(dst, ir->conditional_mod, src[0], src[1]);
1026 break;
1027 case BRW_OPCODE_SEL:
1028 SEL(dst, src[0], src[1]);
1029 break;
1030
1031 case BRW_OPCODE_BFREV:
1032 /* BFREV only supports UD type for src and dst. */
1033 BFREV(retype(dst, BRW_REGISTER_TYPE_UD),
1034 retype(src[0], BRW_REGISTER_TYPE_UD));
1035 break;
1036
1037 case BRW_OPCODE_FBH:
1038 /* FBH only supports UD type for dst. */
1039 FBH(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1040 break;
1041
1042 case BRW_OPCODE_FBL:
1043 /* FBL only supports UD type for dst. */
1044 FBL(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1045 break;
1046
1047 case BRW_OPCODE_CBIT:
1048 /* CBIT only supports UD type for dst. */
1049 CBIT(retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1050 break;
1051
1052 case BRW_OPCODE_ADDC:
1053 ADDC(dst, src[0], src[1]);
1054 break;
1055
1056 case BRW_OPCODE_SUBB:
1057 SUBB(dst, src[0], src[1]);
1058 break;
1059
1060 case BRW_OPCODE_BFE:
1061 default_state.access_mode = BRW_ALIGN_16;
1062 BFE(dst, src[0], src[1], src[2]);
1063 default_state.access_mode = BRW_ALIGN_1;
1064 break;
1065
1066 case BRW_OPCODE_BFI1:
1067 BFI1(dst, src[0], src[1]);
1068 break;
1069
1070 case BRW_OPCODE_BFI2:
1071 default_state.access_mode = BRW_ALIGN_16;
1072 BFI2(dst, src[0], src[1], src[2]);
1073 default_state.access_mode = BRW_ALIGN_1;
1074 break;
1075
1076 case BRW_OPCODE_IF:
1077 IF(BRW_PREDICATE_NORMAL);
1078 break;
1079
1080 case BRW_OPCODE_ELSE:
1081 ELSE();
1082 break;
1083
1084 case BRW_OPCODE_ENDIF:
1085 ENDIF();
1086 break;
1087
1088 case BRW_OPCODE_DO:
1089 DO();
1090 break;
1091
1092 case BRW_OPCODE_BREAK:
1093 BREAK();
1094 break;
1095
1096 case BRW_OPCODE_CONTINUE:
1097 CONTINUE();
1098 break;
1099
1100 case BRW_OPCODE_WHILE:
1101 WHILE();
1102 break;
1103
1104 case SHADER_OPCODE_RCP:
1105 MATH(BRW_MATH_FUNCTION_INV, dst, src[0]);
1106 break;
1107
1108 case SHADER_OPCODE_RSQ:
1109 MATH(BRW_MATH_FUNCTION_RSQ, dst, src[0]);
1110 break;
1111
1112 case SHADER_OPCODE_SQRT:
1113 MATH(BRW_MATH_FUNCTION_SQRT, dst, src[0]);
1114 break;
1115
1116 case SHADER_OPCODE_EXP2:
1117 MATH(BRW_MATH_FUNCTION_EXP, dst, src[0]);
1118 break;
1119
1120 case SHADER_OPCODE_LOG2:
1121 MATH(BRW_MATH_FUNCTION_LOG, dst, src[0]);
1122 break;
1123
1124 case SHADER_OPCODE_SIN:
1125 MATH(BRW_MATH_FUNCTION_SIN, dst, src[0]);
1126 break;
1127
1128 case SHADER_OPCODE_COS:
1129 MATH(BRW_MATH_FUNCTION_COS, dst, src[0]);
1130 break;
1131
1132 case SHADER_OPCODE_INT_QUOTIENT:
1133 MATH(BRW_MATH_FUNCTION_INT_DIV_QUOTIENT, dst, src[0], src[1]);
1134 break;
1135
1136 case SHADER_OPCODE_INT_REMAINDER:
1137 MATH(BRW_MATH_FUNCTION_INT_DIV_REMAINDER, dst, src[0], src[1]);
1138 break;
1139
1140 case SHADER_OPCODE_POW:
1141 MATH(BRW_MATH_FUNCTION_POW, dst, src[0], src[1]);
1142 break;
1143
1144 case FS_OPCODE_PIXEL_X:
1145 case FS_OPCODE_PIXEL_Y:
1146 assert(!"FS_OPCODE_PIXEL_X and FS_OPCODE_PIXEL_Y are only for Gen4-5.");
1147 break;
1148
1149 case FS_OPCODE_CINTERP:
1150 MOV(dst, src[0]);
1151 break;
1152 case FS_OPCODE_LINTERP:
1153 generate_linterp(ir, dst, src);
1154 break;
1155 case SHADER_OPCODE_TEX:
1156 case FS_OPCODE_TXB:
1157 case SHADER_OPCODE_TXD:
1158 case SHADER_OPCODE_TXF:
1159 case SHADER_OPCODE_TXF_CMS:
1160 case SHADER_OPCODE_TXF_UMS:
1161 case SHADER_OPCODE_TXF_MCS:
1162 case SHADER_OPCODE_TXL:
1163 case SHADER_OPCODE_TXS:
1164 case SHADER_OPCODE_LOD:
1165 case SHADER_OPCODE_TG4:
1166 case SHADER_OPCODE_TG4_OFFSET:
1167 generate_tex(ir, dst, src[0]);
1168 break;
1169
1170 case FS_OPCODE_DDX:
1171 generate_ddx(ir, dst, src[0]);
1172 break;
1173 case FS_OPCODE_DDY:
1174 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1175 * guarantee that c->key.render_to_fbo is set).
1176 */
1177 assert(fp->UsesDFdy);
1178 generate_ddy(ir, dst, src[0], c->key.render_to_fbo);
1179 break;
1180
1181 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1182 generate_scratch_write(ir, src[0]);
1183 break;
1184
1185 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1186 generate_scratch_read(ir, dst);
1187 break;
1188
1189 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1190 generate_scratch_read_gen7(ir, dst);
1191 break;
1192
1193 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1194 generate_uniform_pull_constant_load(ir, dst, src[0], src[1]);
1195 break;
1196
1197 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1198 generate_varying_pull_constant_load(ir, dst, src[0], src[1]);
1199 break;
1200
1201 case FS_OPCODE_FB_WRITE:
1202 generate_fb_write(ir);
1203 break;
1204
1205 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1206 generate_mov_dispatch_to_flags(ir);
1207 break;
1208
1209 case FS_OPCODE_DISCARD_JUMP:
1210 generate_discard_jump(ir);
1211 break;
1212
1213 case SHADER_OPCODE_SHADER_TIME_ADD:
1214 assert(!"XXX: Missing Gen8 scalar support for INTEL_DEBUG=shader_time");
1215 break;
1216
1217 case SHADER_OPCODE_UNTYPED_ATOMIC:
1218 assert(!"XXX: Missing Gen8 scalar support for untyped atomics");
1219 break;
1220
1221 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1222 generate_untyped_surface_read(ir, dst, src[0]);
1223 break;
1224
1225 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1226 generate_set_simd4x2_offset(ir, dst, src[0]);
1227 break;
1228
1229 case FS_OPCODE_SET_OMASK:
1230 generate_set_omask(ir, dst, src[0]);
1231 break;
1232
1233 case FS_OPCODE_SET_SAMPLE_ID:
1234 generate_set_sample_id(ir, dst, src[0], src[1]);
1235 break;
1236
1237 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1238 generate_pack_half_2x16_split(ir, dst, src[0], src[1]);
1239 break;
1240
1241 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1242 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1243 generate_unpack_half_2x16_split(ir, dst, src[0]);
1244 break;
1245
1246 case FS_OPCODE_PLACEHOLDER_HALT:
1247 /* This is the place where the final HALT needs to be inserted if
1248 * we've emitted any discards. If not, this will emit no code.
1249 */
1250 patch_discard_jumps_to_fb_writes();
1251 break;
1252
1253 default:
1254 if (ir->opcode < int(ARRAY_SIZE(opcode_descs))) {
1255 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1256 opcode_descs[ir->opcode].name);
1257 } else {
1258 _mesa_problem(ctx, "Unsupported opcode %d in FS", ir->opcode);
1259 }
1260 abort();
1261 }
1262
1263 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1264 disassemble(stderr, last_native_inst_offset, next_inst_offset);
1265
1266 foreach_list(node, &cfg->block_list) {
1267 bblock_link *link = (bblock_link *)node;
1268 bblock_t *block = link->block;
1269
1270 if (block->end == ir) {
1271 fprintf(stderr, " END B%d", block->block_num);
1272 foreach_list(successor_node, &block->children) {
1273 bblock_link *successor_link =
1274 (bblock_link *)successor_node;
1275 bblock_t *successor_block = successor_link->block;
1276 fprintf(stderr, " ->B%d", successor_block->block_num);
1277 }
1278 fprintf(stderr, "\n");
1279 }
1280 }
1281 }
1282
1283 last_native_inst_offset = next_inst_offset;
1284 }
1285
1286 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1287 fprintf(stderr, "\n");
1288 }
1289
1290 patch_jump_targets();
1291
1292 /* OK, while the INTEL_DEBUG=fs above is very nice for debugging FS
1293 * emit issues, it doesn't get the jump distances into the output,
1294 * which is often something we want to debug. So this is here in
1295 * case you're doing that.
1296 */
1297 if (0 && unlikely(INTEL_DEBUG & DEBUG_WM)) {
1298 disassemble(stderr, 0, next_inst_offset);
1299 }
1300 }
1301
1302 const unsigned *
1303 gen8_fs_generator::generate_assembly(exec_list *simd8_instructions,
1304 exec_list *simd16_instructions,
1305 unsigned *assembly_size)
1306 {
1307 assert(simd8_instructions || simd16_instructions);
1308
1309 if (simd8_instructions) {
1310 dispatch_width = 8;
1311 generate_code(simd8_instructions);
1312 }
1313
1314 if (simd16_instructions) {
1315 /* Align to a 64-byte boundary. */
1316 while ((nr_inst * sizeof(gen8_instruction)) % 64)
1317 NOP();
1318
1319 /* Save off the start of this SIMD16 program */
1320 c->prog_data.prog_offset_16 = nr_inst * sizeof(gen8_instruction);
1321
1322 dispatch_width = 16;
1323 generate_code(simd16_instructions);
1324 }
1325
1326 *assembly_size = next_inst_offset;
1327 return (const unsigned *) store;
1328 }