i965: Enable EGL_KHR_gl_texture_3D_image
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_gs_state.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "intel_batchbuffer.h"
28
29 static void
30 gen8_upload_gs_state(struct brw_context *brw)
31 {
32 const struct gen_device_info *devinfo = &brw->screen->devinfo;
33 struct gl_context *ctx = &brw->ctx;
34 const struct brw_stage_state *stage_state = &brw->gs.base;
35 /* BRW_NEW_GEOMETRY_PROGRAM */
36 bool active = brw->geometry_program;
37 /* BRW_NEW_GS_PROG_DATA */
38 const struct brw_vue_prog_data *prog_data = &brw->gs.prog_data->base;
39
40 if (active) {
41 int urb_entry_write_offset = 1;
42 uint32_t urb_entry_output_length =
43 ((prog_data->vue_map.num_slots + 1) / 2 - urb_entry_write_offset);
44
45 if (urb_entry_output_length == 0)
46 urb_entry_output_length = 1;
47
48 BEGIN_BATCH(10);
49 OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
50 OUT_BATCH(stage_state->prog_offset);
51 OUT_BATCH(0);
52 OUT_BATCH(brw->gs.prog_data->vertices_in |
53 ((ALIGN(stage_state->sampler_count, 4)/4) <<
54 GEN6_GS_SAMPLER_COUNT_SHIFT) |
55 ((prog_data->base.binding_table.size_bytes / 4) <<
56 GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
57
58 if (brw->gs.prog_data->base.base.total_scratch) {
59 OUT_RELOC64(stage_state->scratch_bo,
60 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
61 ffs(stage_state->per_thread_scratch) - 11);
62 } else {
63 OUT_BATCH(0);
64 OUT_BATCH(0);
65 }
66
67 /* DW6 */
68 OUT_BATCH(((brw->gs.prog_data->output_vertex_size_hwords * 2 - 1) <<
69 GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT) |
70 (brw->gs.prog_data->output_topology <<
71 GEN7_GS_OUTPUT_TOPOLOGY_SHIFT) |
72 (prog_data->include_vue_handles ?
73 GEN7_GS_INCLUDE_VERTEX_HANDLES : 0) |
74 (prog_data->urb_read_length <<
75 GEN6_GS_URB_READ_LENGTH_SHIFT) |
76 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
77 (prog_data->base.dispatch_grf_start_reg <<
78 GEN6_GS_DISPATCH_START_GRF_SHIFT));
79
80 uint32_t dw7 = (brw->gs.prog_data->control_data_header_size_hwords <<
81 GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT) |
82 SET_FIELD(prog_data->dispatch_mode,
83 GEN7_GS_DISPATCH_MODE) |
84 ((brw->gs.prog_data->invocations - 1) <<
85 GEN7_GS_INSTANCE_CONTROL_SHIFT) |
86 GEN6_GS_STATISTICS_ENABLE |
87 (brw->gs.prog_data->include_primitive_id ?
88 GEN7_GS_INCLUDE_PRIMITIVE_ID : 0) |
89 GEN7_GS_REORDER_TRAILING |
90 GEN7_GS_ENABLE;
91 uint32_t dw8 = brw->gs.prog_data->control_data_format <<
92 HSW_GS_CONTROL_DATA_FORMAT_SHIFT;
93
94 if (brw->gs.prog_data->static_vertex_count != -1) {
95 dw8 |= GEN8_GS_STATIC_OUTPUT |
96 SET_FIELD(brw->gs.prog_data->static_vertex_count,
97 GEN8_GS_STATIC_VERTEX_COUNT);
98 }
99
100 if (brw->gen < 9)
101 dw7 |= (devinfo->max_gs_threads / 2 - 1) << HSW_GS_MAX_THREADS_SHIFT;
102 else
103 dw8 |= devinfo->max_gs_threads - 1;
104
105 /* DW7 */
106 OUT_BATCH(dw7);
107
108 /* DW8 */
109 OUT_BATCH(dw8);
110
111 /* DW9 / _NEW_TRANSFORM */
112 OUT_BATCH((prog_data->cull_distance_mask |
113 ctx->Transform.ClipPlanesEnabled <<
114 GEN8_GS_USER_CLIP_DISTANCE_SHIFT) |
115 (urb_entry_output_length << GEN8_GS_URB_OUTPUT_LENGTH_SHIFT) |
116 (urb_entry_write_offset <<
117 GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT));
118 ADVANCE_BATCH();
119 } else {
120 BEGIN_BATCH(10);
121 OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
122 OUT_BATCH(0); /* prog_bo */
123 OUT_BATCH(0);
124 OUT_BATCH(0);
125 OUT_BATCH(0); /* scratch space base offset */
126 OUT_BATCH(0);
127 OUT_BATCH(0);
128 OUT_BATCH(GEN6_GS_STATISTICS_ENABLE);
129 OUT_BATCH(0);
130 OUT_BATCH(0);
131 ADVANCE_BATCH();
132 }
133 }
134
135 const struct brw_tracked_state gen8_gs_state = {
136 .dirty = {
137 .mesa = _NEW_TRANSFORM,
138 .brw = BRW_NEW_BATCH |
139 BRW_NEW_BLORP |
140 BRW_NEW_CONTEXT |
141 BRW_NEW_GEOMETRY_PROGRAM |
142 BRW_NEW_GS_PROG_DATA,
143 },
144 .emit = gen8_upload_gs_state,
145 };