src/mesa/drivers/dri/i965/gen8_misc_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28
  29 /**
  30  * Define the base addresses which some state is referenced from.
  31  */
  32 static void upload_state_base_address(struct brw_context *brw)
  33 {
  34    perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
  35
  36    BEGIN_BATCH(16);
  37    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2));
  38    /* General state base address: stateless DP read/write requests */
  39    OUT_BATCH(0);
  40    OUT_BATCH(BDW_MOCS_WB << 2 | 1);
  41    OUT_BATCH(BDW_MOCS_WB << 16);
  42    /* Surface state base address: */
  43    OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
  44                BDW_MOCS_WB << 4 | 1);
  45    /* Dynamic state base address: */
  46    OUT_RELOC64(brw->batch.bo,
  47                I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
  48                BDW_MOCS_WB << 4 | 1);
  49    /* Indirect object base address: MEDIA_OBJECT data */
  50    OUT_BATCH(0);
  51    OUT_BATCH(BDW_MOCS_WB << 4 | 1);
  52    /* Instruction base address: shader kernels (incl. SIP) */
  53    OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  54                BDW_MOCS_WB << 4 | 1);
  55
  56    /* General state buffer size */
  57    OUT_BATCH(0xfffff001);
  58    /* Dynamic state buffer size */
  59    OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
  60    /* Indirect object upper bound */
  61    OUT_BATCH(0xfffff001);
  62    /* Instruction access upper bound */
  63    OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
  64    ADVANCE_BATCH();
  65
  66    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
  67 }
  68
  69 const struct brw_tracked_state gen8_state_base_address = {
  70    .dirty = {
  71       .mesa = 0,
  72       .brw = BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE,
  73       .cache = 0,
  74    },
  75    .emit = upload_state_base_address
  76 };