2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "intel_batchbuffer.h"
26 #include "brw_context.h"
27 #include "brw_defines.h"
28 #include "brw_multisample_state.h"
31 * From Gen10 Workarounds page in h/w specs:
33 * Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
34 * markers in the pipeline by programming a PIPE_CONTROL with stall.
37 gen10_emit_wa_cs_stall_flush(struct brw_context
*brw
)
39 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
40 assert(devinfo
->gen
== 10);
41 brw_emit_pipe_control_flush(brw
,
42 PIPE_CONTROL_CS_STALL
|
43 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
47 * From Gen10 Workarounds page in h/w specs:
49 * When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
50 * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
51 * after the command to ensure the state has been delivered prior to any
52 * command causing a marker in the pipeline.
55 gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context
*brw
)
57 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
58 assert(devinfo
->gen
== 10);
60 /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
61 * be idle; i.e., full flush is required.
63 brw_emit_pipe_control_flush(brw
,
64 PIPE_CONTROL_CACHE_FLUSH_BITS
|
65 PIPE_CONTROL_CACHE_INVALIDATE_BITS
);
67 /* Write to CACHE_MODE_0 (0x7000) */
68 brw_load_register_imm32(brw
, GEN7_CACHE_MODE_0
, 0);
72 * 3DSTATE_SAMPLE_PATTERN
75 gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
)
77 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
79 if (devinfo
->gen
== 10)
80 gen10_emit_wa_cs_stall_flush(brw
);
83 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN
<< 16 | (9 - 2));
86 OUT_BATCH(brw_multisample_positions_16x
[0]); /* positions 3, 2, 1, 0 */
87 OUT_BATCH(brw_multisample_positions_16x
[1]); /* positions 7, 6, 5, 4 */
88 OUT_BATCH(brw_multisample_positions_16x
[2]); /* positions 11, 10, 9, 8 */
89 OUT_BATCH(brw_multisample_positions_16x
[3]); /* positions 15, 14, 13, 12 */
92 OUT_BATCH(brw_multisample_positions_8x
[1]); /* sample positions 7654 */
93 OUT_BATCH(brw_multisample_positions_8x
[0]); /* sample positions 3210 */
96 OUT_BATCH(brw_multisample_positions_4x
);
99 OUT_BATCH(brw_multisample_positions_1x_2x
);
102 if (devinfo
->gen
== 10)
103 gen10_emit_wa_lri_to_cache_mode_zero(brw
);