src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_wm.h"
  29 #include "intel_batchbuffer.h"
  30
  31 void
  32 gen8_upload_ps_extra(struct brw_context *brw,
  33                      const struct brw_wm_prog_data *prog_data)
  34 {
  35    uint32_t dw1 = 0;
  36
  37    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  38    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  39
  40    if (prog_data->uses_kill)
  41       dw1 |= GEN8_PSX_KILL_ENABLE;
  42
  43    if (prog_data->num_varying_inputs != 0)
  44       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  45
  46    if (prog_data->uses_src_depth)
  47       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
  48
  49    if (prog_data->uses_src_w)
  50       dw1 |= GEN8_PSX_USES_SOURCE_W;
  51
  52    if (prog_data->persample_dispatch)
  53       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  54
  55    if (prog_data->uses_sample_mask) {
  56       if (brw->gen >= 9)
  57          dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
  58       else
  59          dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  60    }
  61
  62    if (prog_data->uses_omask)
  63       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  64
  65    if (brw->gen >= 9 && prog_data->pulls_bary)
  66       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  67
  68    /* The stricter cross-primitive coherency guarantees that the hardware
  69     * gives us with the "Accesses UAV" bit set for at least one shader stage
  70     * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
  71     * redundant within the current image, atomic counter and SSBO GL APIs,
  72     * which all have very loose ordering and coherency requirements and
  73     * generally rely on the application to insert explicit barriers when a
  74     * shader invocation is expected to see the memory writes performed by the
  75     * invocations of some previous primitive.  Regardless of the value of "UAV
  76     * coherency required", the "Accesses UAV" bits will implicitly cause an in
  77     * most cases useless DC flush when the lowermost stage with the bit set
  78     * finishes execution.
  79     *
  80     * It would be nice to disable it, but in some cases we can't because on
  81     * Gen8+ it also has an influence on rasterization via the PS UAV-only
  82     * signal (which could be set independently from the coherency mechanism in
  83     * the 3DSTATE_WM command on Gen7), and because in some cases it will
  84     * determine whether the hardware skips execution of the fragment shader or
  85     * not via the ThreadDispatchEnable signal.  However if we know that
  86     * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
  87     * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
  88     * difference so we may just disable it here.
  89     *
  90     * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
  91     * take into account KillPixels when no depth or stencil writes are enabled.
  92     * In order for occlusion queries to work correctly with no attachments, we
  93     * need to force-enable here.
  94     *
  95     * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
  96     */
  97    if ((prog_data->has_side_effects || prog_data->uses_kill) &&
  98        !brw_color_buffer_write_enabled(brw))
  99       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
 100
 101    if (prog_data->computed_stencil) {
 102       assert(brw->gen >= 9);
 103       dw1 |= GEN9_PSX_SHADER_COMPUTES_STENCIL;
 104    }
 105
 106    BEGIN_BATCH(2);
 107    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
 108    OUT_BATCH(dw1);
 109    ADVANCE_BATCH();
 110 }
 111
 112 static void
 113 upload_ps_extra(struct brw_context *brw)
 114 {
 115    /* BRW_NEW_FS_PROG_DATA */
 116    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 117
 118    gen8_upload_ps_extra(brw, prog_data);
 119 }
 120
 121 const struct brw_tracked_state gen8_ps_extra = {
 122    .dirty = {
 123       .mesa  = _NEW_BUFFERS | _NEW_COLOR,
 124       .brw   = BRW_NEW_BLORP |
 125                BRW_NEW_CONTEXT |
 126                BRW_NEW_FS_PROG_DATA,
 127    },
 128    .emit = upload_ps_extra,
 129 };
 130
 131 static void
 132 upload_wm_state(struct brw_context *brw)
 133 {
 134    struct gl_context *ctx = &brw->ctx;
 135    uint32_t dw1 = 0;
 136
 137    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 138    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 139    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 140    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 141
 142    /* _NEW_LINE */
 143    if (ctx->Line.StippleFlag)
 144       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 145
 146    /* _NEW_POLYGON */
 147    if (ctx->Polygon.StippleFlag)
 148       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 149
 150    /* BRW_NEW_FS_PROG_DATA */
 151    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 152       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 153
 154    /* BRW_NEW_FS_PROG_DATA */
 155    if (brw->wm.prog_data->early_fragment_tests)
 156       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 157    else if (brw->wm.prog_data->has_side_effects)
 158       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 159
 160    BEGIN_BATCH(2);
 161    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 162    OUT_BATCH(dw1);
 163    ADVANCE_BATCH();
 164 }
 165
 166 const struct brw_tracked_state gen8_wm_state = {
 167    .dirty = {
 168       .mesa  = _NEW_LINE |
 169                _NEW_POLYGON,
 170       .brw   = BRW_NEW_BLORP |
 171                BRW_NEW_CONTEXT |
 172                BRW_NEW_FS_PROG_DATA,
 173    },
 174    .emit = upload_wm_state,
 175 };
 176
 177 void
 178 gen8_upload_ps_state(struct brw_context *brw,
 179                      const struct brw_stage_state *stage_state,
 180                      const struct brw_wm_prog_data *prog_data,
 181                      uint32_t fast_clear_op)
 182 {
 183    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 184
 185    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 186     * incorrect for subspans where some of the pixels are unlit.  We believe
 187     * the bit just didn't take effect in previous generations.
 188     */
 189    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 190
 191    const unsigned sampler_count =
 192       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 193    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 194
 195    /* BRW_NEW_FS_PROG_DATA */
 196    dw3 |=
 197       ((prog_data->base.binding_table.size_bytes / 4) <<
 198        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 199
 200    if (prog_data->base.use_alt_mode)
 201       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 202
 203    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 204     * it implicitly scales for different GT levels (which have some # of PSDs).
 205     *
 206     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 207     */
 208    if (brw->gen >= 9)
 209       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 210    else
 211       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 212
 213    if (prog_data->base.nr_params > 0)
 214       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 215
 216    /* From the documentation for this packet:
 217     * "If the PS kernel does not need the Position XY Offsets to
 218     *  compute a Position Value, then this field should be programmed
 219     *  to POSOFFSET_NONE."
 220     *
 221     * "SW Recommendation: If the PS kernel needs the Position Offsets
 222     *  to compute a Position XY value, this field should match Position
 223     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 224     *  computation."
 225     *
 226     * We only require XY sample offsets. So, this recommendation doesn't
 227     * look useful at the moment. We might need this in future.
 228     */
 229    if (prog_data->uses_pos_offset)
 230       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 231    else
 232       dw6 |= GEN7_PS_POSOFFSET_NONE;
 233
 234    dw6 |= fast_clear_op;
 235
 236    if (prog_data->dispatch_8)
 237       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 238
 239    if (prog_data->dispatch_16)
 240       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 241
 242    dw7 |= prog_data->base.dispatch_grf_start_reg <<
 243           GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 244    dw7 |= prog_data->dispatch_grf_start_reg_2 <<
 245           GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 246
 247    ksp0 = stage_state->prog_offset;
 248    ksp2 = stage_state->prog_offset + prog_data->prog_offset_2;
 249
 250    BEGIN_BATCH(12);
 251    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 252    OUT_BATCH(ksp0);
 253    OUT_BATCH(0);
 254    OUT_BATCH(dw3);
 255    if (prog_data->base.total_scratch) {
 256       OUT_RELOC64(stage_state->scratch_bo,
 257                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 258                   ffs(stage_state->per_thread_scratch) - 11);
 259    } else {
 260       OUT_BATCH(0);
 261       OUT_BATCH(0);
 262    }
 263    OUT_BATCH(dw6);
 264    OUT_BATCH(dw7);
 265    OUT_BATCH(0); /* kernel 1 pointer */
 266    OUT_BATCH(0);
 267    OUT_BATCH(ksp2);
 268    OUT_BATCH(0);
 269    ADVANCE_BATCH();
 270 }
 271
 272 static void
 273 upload_ps_state(struct brw_context *brw)
 274 {
 275    /* BRW_NEW_FS_PROG_DATA */
 276    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 277    gen8_upload_ps_state(brw, &brw->wm.base, prog_data, brw->wm.fast_clear_op);
 278 }
 279
 280 const struct brw_tracked_state gen8_ps_state = {
 281    .dirty = {
 282       .mesa  = _NEW_MULTISAMPLE,
 283       .brw   = BRW_NEW_BATCH |
 284                BRW_NEW_BLORP |
 285                BRW_NEW_FRAGMENT_PROGRAM |
 286                BRW_NEW_FS_PROG_DATA,
 287    },
 288    .emit = upload_ps_state,
 289 };