2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "program/program.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
29 #include "intel_batchbuffer.h"
32 gen8_upload_ps_extra(struct brw_context
*brw
,
33 const struct gl_fragment_program
*fp
,
34 const struct brw_wm_prog_data
*prog_data
,
35 bool multisampled_fbo
)
37 struct gl_context
*ctx
= &brw
->ctx
;
40 dw1
|= GEN8_PSX_PIXEL_SHADER_VALID
;
41 dw1
|= prog_data
->computed_depth_mode
<< GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT
;
43 if (prog_data
->uses_kill
)
44 dw1
|= GEN8_PSX_KILL_ENABLE
;
46 if (prog_data
->num_varying_inputs
!= 0)
47 dw1
|= GEN8_PSX_ATTRIBUTE_ENABLE
;
49 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
)
50 dw1
|= GEN8_PSX_USES_SOURCE_DEPTH
| GEN8_PSX_USES_SOURCE_W
;
52 if (multisampled_fbo
&&
53 _mesa_get_min_invocations_per_fragment(ctx
, fp
, false) > 1)
54 dw1
|= GEN8_PSX_SHADER_IS_PER_SAMPLE
;
56 if (fp
->Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
58 dw1
|= BRW_PSICMS_INNER
<< GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT
;
60 dw1
|= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK
;
63 if (prog_data
->uses_omask
)
64 dw1
|= GEN8_PSX_OMASK_TO_RENDER_TARGET
;
66 if (brw
->gen
>= 9 && prog_data
->pulls_bary
)
67 dw1
|= GEN9_PSX_SHADER_PULLS_BARY
;
69 /* The stricter cross-primitive coherency guarantees that the hardware
70 * gives us with the "Accesses UAV" bit set for at least one shader stage
71 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
72 * redundant within the current image, atomic counter and SSBO GL APIs,
73 * which all have very loose ordering and coherency requirements and
74 * generally rely on the application to insert explicit barriers when a
75 * shader invocation is expected to see the memory writes performed by the
76 * invocations of some previous primitive. Regardless of the value of "UAV
77 * coherency required", the "Accesses UAV" bits will implicitly cause an in
78 * most cases useless DC flush when the lowermost stage with the bit set
81 * It would be nice to disable it, but in some cases we can't because on
82 * Gen8+ it also has an influence on rasterization via the PS UAV-only
83 * signal (which could be set independently from the coherency mechanism in
84 * the 3DSTATE_WM command on Gen7), and because in some cases it will
85 * determine whether the hardware skips execution of the fragment shader or
86 * not via the ThreadDispatchEnable signal. However if we know that
87 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
88 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
89 * difference so we may just disable it here.
91 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
93 if ((_mesa_active_fragment_shader_has_atomic_ops(&brw
->ctx
) ||
94 prog_data
->base
.nr_image_params
) &&
95 !brw_color_buffer_write_enabled(brw
))
96 dw1
|= GEN8_PSX_SHADER_HAS_UAV
;
98 if (prog_data
->computed_stencil
) {
99 assert(brw
->gen
>= 9);
100 dw1
|= GEN9_PSX_SHADER_COMPUTES_STENCIL
;
104 OUT_BATCH(_3DSTATE_PS_EXTRA
<< 16 | (2 - 2));
110 upload_ps_extra(struct brw_context
*brw
)
112 /* BRW_NEW_FRAGMENT_PROGRAM */
113 const struct brw_fragment_program
*fp
=
114 brw_fragment_program_const(brw
->fragment_program
);
115 /* BRW_NEW_FS_PROG_DATA */
116 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
117 /* BRW_NEW_NUM_SAMPLES */
118 const bool multisampled_fbo
= brw
->num_samples
> 1;
120 gen8_upload_ps_extra(brw
, &fp
->program
, prog_data
, multisampled_fbo
);
123 const struct brw_tracked_state gen8_ps_extra
= {
125 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
126 .brw
= BRW_NEW_CONTEXT
|
127 BRW_NEW_FRAGMENT_PROGRAM
|
128 BRW_NEW_FS_PROG_DATA
|
131 .emit
= upload_ps_extra
,
135 upload_wm_state(struct brw_context
*brw
)
137 struct gl_context
*ctx
= &brw
->ctx
;
140 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
141 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
142 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
143 dw1
|= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT
;
146 if (ctx
->Line
.StippleFlag
)
147 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
150 if (ctx
->Polygon
.StippleFlag
)
151 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
153 /* BRW_NEW_FS_PROG_DATA */
154 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
155 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
157 /* BRW_NEW_FS_PROG_DATA */
158 if (brw
->wm
.prog_data
->early_fragment_tests
)
159 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PREPS
;
160 else if (brw
->wm
.prog_data
->base
.nr_image_params
)
161 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PSEXEC
;
164 OUT_BATCH(_3DSTATE_WM
<< 16 | (2 - 2));
169 const struct brw_tracked_state gen8_wm_state
= {
173 .brw
= BRW_NEW_CONTEXT
|
174 BRW_NEW_FS_PROG_DATA
,
176 .emit
= upload_wm_state
,
180 gen8_upload_ps_state(struct brw_context
*brw
,
181 const struct gl_fragment_program
*fp
,
182 const struct brw_stage_state
*stage_state
,
183 const struct brw_wm_prog_data
*prog_data
,
184 uint32_t fast_clear_op
)
186 struct gl_context
*ctx
= &brw
->ctx
;
187 uint32_t dw3
= 0, dw6
= 0, dw7
= 0, ksp0
, ksp2
= 0;
189 /* Initialize the execution mask with VMask. Otherwise, derivatives are
190 * incorrect for subspans where some of the pixels are unlit. We believe
191 * the bit just didn't take effect in previous generations.
193 dw3
|= GEN7_PS_VECTOR_MASK_ENABLE
;
195 const unsigned sampler_count
=
196 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
197 dw3
|= SET_FIELD(sampler_count
, GEN7_PS_SAMPLER_COUNT
);
199 /* BRW_NEW_FS_PROG_DATA */
201 ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
202 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
204 if (prog_data
->base
.use_alt_mode
)
205 dw3
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
207 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
208 * it implicitly scales for different GT levels (which have some # of PSDs).
210 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
213 dw6
|= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT
;
215 dw6
|= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT
;
217 if (prog_data
->base
.nr_params
> 0)
218 dw6
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
220 /* From the documentation for this packet:
221 * "If the PS kernel does not need the Position XY Offsets to
222 * compute a Position Value, then this field should be programmed
223 * to POSOFFSET_NONE."
225 * "SW Recommendation: If the PS kernel needs the Position Offsets
226 * to compute a Position XY value, this field should match Position
227 * ZW Interpolation Mode to ensure a consistent position.xyzw
230 * We only require XY sample offsets. So, this recommendation doesn't
231 * look useful at the moment. We might need this in future.
233 if (prog_data
->uses_pos_offset
)
234 dw6
|= GEN7_PS_POSOFFSET_SAMPLE
;
236 dw6
|= GEN7_PS_POSOFFSET_NONE
;
238 dw6
|= fast_clear_op
;
241 * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
242 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
243 * is successfully compiled. In majority of the cases that bring us
244 * better performance than 'SIMD8 only' dispatch.
246 int min_invocations_per_fragment
=
247 _mesa_get_min_invocations_per_fragment(ctx
, fp
, false);
248 assert(min_invocations_per_fragment
>= 1);
250 if (prog_data
->prog_offset_16
|| prog_data
->no_8
) {
251 dw6
|= GEN7_PS_16_DISPATCH_ENABLE
;
252 if (!prog_data
->no_8
&& min_invocations_per_fragment
== 1) {
253 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
254 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
255 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
256 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
257 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
258 ksp0
= stage_state
->prog_offset
;
259 ksp2
= stage_state
->prog_offset
+ prog_data
->prog_offset_16
;
261 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
262 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
264 ksp0
= stage_state
->prog_offset
+ prog_data
->prog_offset_16
;
267 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
268 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
269 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
270 ksp0
= stage_state
->prog_offset
;
274 OUT_BATCH(_3DSTATE_PS
<< 16 | (12 - 2));
278 if (prog_data
->base
.total_scratch
) {
279 OUT_RELOC64(stage_state
->scratch_bo
,
280 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
281 ffs(prog_data
->base
.total_scratch
) - 11);
288 OUT_BATCH(0); /* kernel 1 pointer */
296 upload_ps_state(struct brw_context
*brw
)
298 /* BRW_NEW_FS_PROG_DATA */
299 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
300 gen8_upload_ps_state(brw
, brw
->fragment_program
, &brw
->wm
.base
, prog_data
,
301 brw
->wm
.fast_clear_op
);
304 const struct brw_tracked_state gen8_ps_state
= {
306 .mesa
= _NEW_MULTISAMPLE
,
307 .brw
= BRW_NEW_BATCH
|
308 BRW_NEW_FRAGMENT_PROGRAM
|
309 BRW_NEW_FS_PROG_DATA
,
311 .emit
= upload_ps_state
,