2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "program/program.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
28 #include "intel_batchbuffer.h"
31 upload_ps_extra(struct brw_context
*brw
)
33 struct gl_context
*ctx
= &brw
->ctx
;
34 /* BRW_NEW_FRAGMENT_PROGRAM */
35 const struct brw_fragment_program
*fp
=
36 brw_fragment_program_const(brw
->fragment_program
);
37 /* BRW_NEW_FS_PROG_DATA */
38 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
41 dw1
|= GEN8_PSX_PIXEL_SHADER_VALID
;
42 dw1
|= prog_data
->computed_depth_mode
<< GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT
;
44 if (prog_data
->uses_kill
)
45 dw1
|= GEN8_PSX_KILL_ENABLE
;
47 if (prog_data
->num_varying_inputs
!= 0)
48 dw1
|= GEN8_PSX_ATTRIBUTE_ENABLE
;
50 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
51 dw1
|= GEN8_PSX_USES_SOURCE_DEPTH
| GEN8_PSX_USES_SOURCE_W
;
53 /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
54 bool multisampled_fbo
= brw
->num_samples
> 1;
55 if (multisampled_fbo
&&
56 _mesa_get_min_invocations_per_fragment(ctx
, &fp
->program
, false) > 1)
57 dw1
|= GEN8_PSX_SHADER_IS_PER_SAMPLE
;
59 if (fp
->program
.Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
)
60 dw1
|= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK
;
62 if (prog_data
->uses_omask
)
63 dw1
|= GEN8_PSX_OMASK_TO_RENDER_TARGET
;
66 OUT_BATCH(_3DSTATE_PS_EXTRA
<< 16 | (2 - 2));
71 const struct brw_tracked_state gen8_ps_extra
= {
73 .mesa
= _NEW_MULTISAMPLE
,
74 .brw
= BRW_NEW_CONTEXT
|
75 BRW_NEW_FRAGMENT_PROGRAM
|
76 BRW_NEW_FS_PROG_DATA
|
79 .emit
= upload_ps_extra
,
83 upload_wm_state(struct brw_context
*brw
)
85 struct gl_context
*ctx
= &brw
->ctx
;
88 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
89 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
90 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
91 dw1
|= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT
;
94 if (ctx
->Line
.StippleFlag
)
95 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
98 if (ctx
->Polygon
.StippleFlag
)
99 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
101 /* BRW_NEW_FS_PROG_DATA */
102 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
103 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
106 OUT_BATCH(_3DSTATE_WM
<< 16 | (2 - 2));
111 const struct brw_tracked_state gen8_wm_state
= {
115 .brw
= BRW_NEW_CONTEXT
|
116 BRW_NEW_FS_PROG_DATA
,
118 .emit
= upload_wm_state
,
122 upload_ps_state(struct brw_context
*brw
)
124 struct gl_context
*ctx
= &brw
->ctx
;
125 uint32_t dw3
= 0, dw6
= 0, dw7
= 0, ksp0
, ksp2
= 0;
127 /* BRW_NEW_FS_PROG_DATA */
128 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
130 /* Initialize the execution mask with VMask. Otherwise, derivatives are
131 * incorrect for subspans where some of the pixels are unlit. We believe
132 * the bit just didn't take effect in previous generations.
134 dw3
|= GEN7_PS_VECTOR_MASK_ENABLE
;
137 (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
139 /* BRW_NEW_FS_PROG_DATA */
141 ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
142 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
144 if (prog_data
->base
.use_alt_mode
)
145 dw3
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
147 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
148 * it implicitly scales for different GT levels (which have some # of PSDs).
150 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
153 dw6
|= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT
;
155 dw6
|= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT
;
157 if (prog_data
->base
.nr_params
> 0)
158 dw6
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
160 /* From the documentation for this packet:
161 * "If the PS kernel does not need the Position XY Offsets to
162 * compute a Position Value, then this field should be programmed
163 * to POSOFFSET_NONE."
165 * "SW Recommendation: If the PS kernel needs the Position Offsets
166 * to compute a Position XY value, this field should match Position
167 * ZW Interpolation Mode to ensure a consistent position.xyzw
170 * We only require XY sample offsets. So, this recommendation doesn't
171 * look useful at the moment. We might need this in future.
173 if (brw
->wm
.prog_data
->uses_pos_offset
)
174 dw6
|= GEN7_PS_POSOFFSET_SAMPLE
;
176 dw6
|= GEN7_PS_POSOFFSET_NONE
;
178 dw6
|= brw
->wm
.fast_clear_op
;
181 * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
182 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
183 * is successfully compiled. In majority of the cases that bring us
184 * better performance than 'SIMD8 only' dispatch.
186 int min_invocations_per_fragment
=
187 _mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false);
188 assert(min_invocations_per_fragment
>= 1);
190 if (prog_data
->prog_offset_16
|| prog_data
->no_8
) {
191 dw6
|= GEN7_PS_16_DISPATCH_ENABLE
;
192 if (!prog_data
->no_8
&& min_invocations_per_fragment
== 1) {
193 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
194 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
195 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
196 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
197 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
198 ksp0
= brw
->wm
.base
.prog_offset
;
199 ksp2
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
201 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
202 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
204 ksp0
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
207 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
208 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
209 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
210 ksp0
= brw
->wm
.base
.prog_offset
;
214 OUT_BATCH(_3DSTATE_PS
<< 16 | (12 - 2));
218 if (prog_data
->base
.total_scratch
) {
219 OUT_RELOC64(brw
->wm
.base
.scratch_bo
,
220 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
221 ffs(prog_data
->base
.total_scratch
) - 11);
228 OUT_BATCH(0); /* kernel 1 pointer */
235 const struct brw_tracked_state gen8_ps_state
= {
237 .mesa
= _NEW_MULTISAMPLE
,
238 .brw
= BRW_NEW_BATCH
|
239 BRW_NEW_FRAGMENT_PROGRAM
|
240 BRW_NEW_FS_PROG_DATA
,
242 .emit
= upload_ps_state
,