src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_wm.h"
  29 #include "intel_batchbuffer.h"
  30
  31 void
  32 gen8_upload_ps_extra(struct brw_context *brw,
  33                      const struct gl_fragment_program *fp,
  34                      const struct brw_wm_prog_data *prog_data,
  35                      bool multisampled_fbo)
  36 {
  37    struct gl_context *ctx = &brw->ctx;
  38    uint32_t dw1 = 0;
  39
  40    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  41    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  42
  43    if (prog_data->uses_kill)
  44       dw1 |= GEN8_PSX_KILL_ENABLE;
  45
  46    if (prog_data->num_varying_inputs != 0)
  47       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  48
  49    if (fp->Base.InputsRead & VARYING_BIT_POS)
  50       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  51
  52    if (multisampled_fbo &&
  53        _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
  54       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  55
  56    if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
  57       if (brw->gen >= 9)
  58          dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
  59       else
  60          dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  61    }
  62
  63    if (prog_data->uses_omask)
  64       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  65
  66    if (brw->gen >= 9 && prog_data->pulls_bary)
  67       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  68
  69    /* The stricter cross-primitive coherency guarantees that the hardware
  70     * gives us with the "Accesses UAV" bit set for at least one shader stage
  71     * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
  72     * redundant within the current image, atomic counter and SSBO GL APIs,
  73     * which all have very loose ordering and coherency requirements and
  74     * generally rely on the application to insert explicit barriers when a
  75     * shader invocation is expected to see the memory writes performed by the
  76     * invocations of some previous primitive.  Regardless of the value of "UAV
  77     * coherency required", the "Accesses UAV" bits will implicitly cause an in
  78     * most cases useless DC flush when the lowermost stage with the bit set
  79     * finishes execution.
  80     *
  81     * It would be nice to disable it, but in some cases we can't because on
  82     * Gen8+ it also has an influence on rasterization via the PS UAV-only
  83     * signal (which could be set independently from the coherency mechanism in
  84     * the 3DSTATE_WM command on Gen7), and because in some cases it will
  85     * determine whether the hardware skips execution of the fragment shader or
  86     * not via the ThreadDispatchEnable signal.  However if we know that
  87     * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
  88     * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
  89     * difference so we may just disable it here.
  90     *
  91     * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
  92     */
  93    if (_mesa_active_fragment_shader_has_side_effects(&brw->ctx) &&
  94        !brw_color_buffer_write_enabled(brw))
  95       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
  96
  97    if (prog_data->computed_stencil) {
  98       assert(brw->gen >= 9);
  99       dw1 |= GEN9_PSX_SHADER_COMPUTES_STENCIL;
 100    }
 101
 102    BEGIN_BATCH(2);
 103    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
 104    OUT_BATCH(dw1);
 105    ADVANCE_BATCH();
 106 }
 107
 108 static void
 109 upload_ps_extra(struct brw_context *brw)
 110 {
 111    /* BRW_NEW_FRAGMENT_PROGRAM */
 112    const struct brw_fragment_program *fp =
 113       brw_fragment_program_const(brw->fragment_program);
 114    /* BRW_NEW_FS_PROG_DATA */
 115    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 116    /* BRW_NEW_NUM_SAMPLES */
 117    const bool multisampled_fbo = brw->num_samples > 1;
 118
 119    gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
 120 }
 121
 122 const struct brw_tracked_state gen8_ps_extra = {
 123    .dirty = {
 124       .mesa  = _NEW_BUFFERS | _NEW_COLOR,
 125       .brw   = BRW_NEW_CONTEXT |
 126                BRW_NEW_FRAGMENT_PROGRAM |
 127                BRW_NEW_FS_PROG_DATA |
 128                BRW_NEW_NUM_SAMPLES,
 129    },
 130    .emit = upload_ps_extra,
 131 };
 132
 133 static void
 134 upload_wm_state(struct brw_context *brw)
 135 {
 136    struct gl_context *ctx = &brw->ctx;
 137    uint32_t dw1 = 0;
 138
 139    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 140    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 141    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 142    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 143
 144    /* _NEW_LINE */
 145    if (ctx->Line.StippleFlag)
 146       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 147
 148    /* _NEW_POLYGON */
 149    if (ctx->Polygon.StippleFlag)
 150       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 151
 152    /* BRW_NEW_FS_PROG_DATA */
 153    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 154       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 155
 156    /* BRW_NEW_FS_PROG_DATA */
 157    if (brw->wm.prog_data->early_fragment_tests)
 158       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 159    else if (_mesa_active_fragment_shader_has_side_effects(&brw->ctx))
 160       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 161
 162    BEGIN_BATCH(2);
 163    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 164    OUT_BATCH(dw1);
 165    ADVANCE_BATCH();
 166 }
 167
 168 const struct brw_tracked_state gen8_wm_state = {
 169    .dirty = {
 170       .mesa  = _NEW_LINE |
 171                _NEW_POLYGON,
 172       .brw   = BRW_NEW_CONTEXT |
 173                BRW_NEW_FS_PROG_DATA,
 174    },
 175    .emit = upload_wm_state,
 176 };
 177
 178 void
 179 gen8_upload_ps_state(struct brw_context *brw,
 180                      const struct gl_fragment_program *fp,
 181                      const struct brw_stage_state *stage_state,
 182                      const struct brw_wm_prog_data *prog_data,
 183                      uint32_t fast_clear_op)
 184 {
 185    struct gl_context *ctx = &brw->ctx;
 186    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 187
 188    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 189     * incorrect for subspans where some of the pixels are unlit.  We believe
 190     * the bit just didn't take effect in previous generations.
 191     */
 192    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 193
 194    const unsigned sampler_count =
 195       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 196    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 197
 198    /* BRW_NEW_FS_PROG_DATA */
 199    dw3 |=
 200       ((prog_data->base.binding_table.size_bytes / 4) <<
 201        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 202
 203    if (prog_data->base.use_alt_mode)
 204       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 205
 206    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 207     * it implicitly scales for different GT levels (which have some # of PSDs).
 208     *
 209     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 210     */
 211    if (brw->gen >= 9)
 212       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 213    else
 214       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 215
 216    if (prog_data->base.nr_params > 0)
 217       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 218
 219    /* From the documentation for this packet:
 220     * "If the PS kernel does not need the Position XY Offsets to
 221     *  compute a Position Value, then this field should be programmed
 222     *  to POSOFFSET_NONE."
 223     *
 224     * "SW Recommendation: If the PS kernel needs the Position Offsets
 225     *  to compute a Position XY value, this field should match Position
 226     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 227     *  computation."
 228     *
 229     * We only require XY sample offsets. So, this recommendation doesn't
 230     * look useful at the moment. We might need this in future.
 231     */
 232    if (prog_data->uses_pos_offset)
 233       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 234    else
 235       dw6 |= GEN7_PS_POSOFFSET_NONE;
 236
 237    dw6 |= fast_clear_op;
 238
 239    /* _NEW_MULTISAMPLE
 240     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 241     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 242     * is successfully compiled. In majority of the cases that bring us
 243     * better performance than 'SIMD8 only' dispatch.
 244     */
 245    int min_invocations_per_fragment =
 246       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 247    assert(min_invocations_per_fragment >= 1);
 248
 249    if (prog_data->prog_offset_16 || prog_data->no_8) {
 250       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 251       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 252          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 253          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 254                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 255          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 256                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 257          ksp0 = stage_state->prog_offset;
 258          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 259       } else {
 260          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 261                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 262
 263          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 264       }
 265    } else {
 266       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 267       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 268               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 269       ksp0 = stage_state->prog_offset;
 270    }
 271
 272    BEGIN_BATCH(12);
 273    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 274    OUT_BATCH(ksp0);
 275    OUT_BATCH(0);
 276    OUT_BATCH(dw3);
 277    if (prog_data->base.total_scratch) {
 278       OUT_RELOC64(stage_state->scratch_bo,
 279                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 280                   ffs(prog_data->base.total_scratch) - 11);
 281    } else {
 282       OUT_BATCH(0);
 283       OUT_BATCH(0);
 284    }
 285    OUT_BATCH(dw6);
 286    OUT_BATCH(dw7);
 287    OUT_BATCH(0); /* kernel 1 pointer */
 288    OUT_BATCH(0);
 289    OUT_BATCH(ksp2);
 290    OUT_BATCH(0);
 291    ADVANCE_BATCH();
 292 }
 293
 294 static void
 295 upload_ps_state(struct brw_context *brw)
 296 {
 297    /* BRW_NEW_FS_PROG_DATA */
 298    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 299    gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 300                         brw->wm.fast_clear_op);
 301 }
 302
 303 const struct brw_tracked_state gen8_ps_state = {
 304    .dirty = {
 305       .mesa  = _NEW_MULTISAMPLE,
 306       .brw   = BRW_NEW_BATCH |
 307                BRW_NEW_FRAGMENT_PROGRAM |
 308                BRW_NEW_FS_PROG_DATA,
 309    },
 310    .emit = upload_ps_state,
 311 };