2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "program/program.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
29 #include "intel_batchbuffer.h"
32 gen8_upload_ps_extra(struct brw_context
*brw
,
33 const struct gl_fragment_program
*fp
,
34 const struct brw_wm_prog_data
*prog_data
,
35 bool multisampled_fbo
)
37 struct gl_context
*ctx
= &brw
->ctx
;
40 dw1
|= GEN8_PSX_PIXEL_SHADER_VALID
;
41 dw1
|= prog_data
->computed_depth_mode
<< GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT
;
43 if (prog_data
->uses_kill
)
44 dw1
|= GEN8_PSX_KILL_ENABLE
;
46 if (prog_data
->num_varying_inputs
!= 0)
47 dw1
|= GEN8_PSX_ATTRIBUTE_ENABLE
;
49 if (prog_data
->uses_src_depth
)
50 dw1
|= GEN8_PSX_USES_SOURCE_DEPTH
;
52 if (prog_data
->uses_src_w
)
53 dw1
|= GEN8_PSX_USES_SOURCE_W
;
55 if (multisampled_fbo
&&
56 _mesa_get_min_invocations_per_fragment(ctx
, fp
, false) > 1)
57 dw1
|= GEN8_PSX_SHADER_IS_PER_SAMPLE
;
59 if (prog_data
->uses_sample_mask
) {
61 dw1
|= BRW_PSICMS_INNER
<< GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT
;
63 dw1
|= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK
;
66 if (prog_data
->uses_omask
)
67 dw1
|= GEN8_PSX_OMASK_TO_RENDER_TARGET
;
69 if (brw
->gen
>= 9 && prog_data
->pulls_bary
)
70 dw1
|= GEN9_PSX_SHADER_PULLS_BARY
;
72 /* The stricter cross-primitive coherency guarantees that the hardware
73 * gives us with the "Accesses UAV" bit set for at least one shader stage
74 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
75 * redundant within the current image, atomic counter and SSBO GL APIs,
76 * which all have very loose ordering and coherency requirements and
77 * generally rely on the application to insert explicit barriers when a
78 * shader invocation is expected to see the memory writes performed by the
79 * invocations of some previous primitive. Regardless of the value of "UAV
80 * coherency required", the "Accesses UAV" bits will implicitly cause an in
81 * most cases useless DC flush when the lowermost stage with the bit set
84 * It would be nice to disable it, but in some cases we can't because on
85 * Gen8+ it also has an influence on rasterization via the PS UAV-only
86 * signal (which could be set independently from the coherency mechanism in
87 * the 3DSTATE_WM command on Gen7), and because in some cases it will
88 * determine whether the hardware skips execution of the fragment shader or
89 * not via the ThreadDispatchEnable signal. However if we know that
90 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
91 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
92 * difference so we may just disable it here.
94 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
95 * take into account KillPixels when no depth or stencil writes are enabled.
96 * In order for occlusion queries to work correctly with no attachments, we
97 * need to force-enable here.
99 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
101 if ((_mesa_active_fragment_shader_has_side_effects(ctx
) ||
102 prog_data
->uses_kill
) && !brw_color_buffer_write_enabled(brw
))
103 dw1
|= GEN8_PSX_SHADER_HAS_UAV
;
105 if (prog_data
->computed_stencil
) {
106 assert(brw
->gen
>= 9);
107 dw1
|= GEN9_PSX_SHADER_COMPUTES_STENCIL
;
111 OUT_BATCH(_3DSTATE_PS_EXTRA
<< 16 | (2 - 2));
117 upload_ps_extra(struct brw_context
*brw
)
119 /* BRW_NEW_FRAGMENT_PROGRAM */
120 const struct brw_fragment_program
*fp
=
121 brw_fragment_program_const(brw
->fragment_program
);
122 /* BRW_NEW_FS_PROG_DATA */
123 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
124 /* BRW_NEW_NUM_SAMPLES */
125 const bool multisampled_fbo
= brw
->num_samples
> 1;
127 gen8_upload_ps_extra(brw
, &fp
->program
, prog_data
, multisampled_fbo
);
130 const struct brw_tracked_state gen8_ps_extra
= {
132 .mesa
= _NEW_BUFFERS
| _NEW_COLOR
,
133 .brw
= BRW_NEW_BLORP
|
135 BRW_NEW_FRAGMENT_PROGRAM
|
136 BRW_NEW_FS_PROG_DATA
|
139 .emit
= upload_ps_extra
,
143 upload_wm_state(struct brw_context
*brw
)
145 struct gl_context
*ctx
= &brw
->ctx
;
148 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
149 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
150 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
151 dw1
|= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT
;
154 if (ctx
->Line
.StippleFlag
)
155 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
158 if (ctx
->Polygon
.StippleFlag
)
159 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
161 /* BRW_NEW_FS_PROG_DATA */
162 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
163 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
165 /* BRW_NEW_FS_PROG_DATA */
166 if (brw
->wm
.prog_data
->early_fragment_tests
)
167 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PREPS
;
168 else if (_mesa_active_fragment_shader_has_side_effects(&brw
->ctx
))
169 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PSEXEC
;
172 OUT_BATCH(_3DSTATE_WM
<< 16 | (2 - 2));
177 const struct brw_tracked_state gen8_wm_state
= {
181 .brw
= BRW_NEW_BLORP
|
183 BRW_NEW_FS_PROG_DATA
,
185 .emit
= upload_wm_state
,
189 gen8_upload_ps_state(struct brw_context
*brw
,
190 const struct gl_fragment_program
*fp
,
191 const struct brw_stage_state
*stage_state
,
192 const struct brw_wm_prog_data
*prog_data
,
193 uint32_t fast_clear_op
)
195 struct gl_context
*ctx
= &brw
->ctx
;
196 uint32_t dw3
= 0, dw6
= 0, dw7
= 0, ksp0
, ksp2
= 0;
198 /* Initialize the execution mask with VMask. Otherwise, derivatives are
199 * incorrect for subspans where some of the pixels are unlit. We believe
200 * the bit just didn't take effect in previous generations.
202 dw3
|= GEN7_PS_VECTOR_MASK_ENABLE
;
204 const unsigned sampler_count
=
205 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
206 dw3
|= SET_FIELD(sampler_count
, GEN7_PS_SAMPLER_COUNT
);
208 /* BRW_NEW_FS_PROG_DATA */
210 ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
211 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
213 if (prog_data
->base
.use_alt_mode
)
214 dw3
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
216 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
217 * it implicitly scales for different GT levels (which have some # of PSDs).
219 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
222 dw6
|= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT
;
224 dw6
|= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT
;
226 if (prog_data
->base
.nr_params
> 0)
227 dw6
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
229 /* From the documentation for this packet:
230 * "If the PS kernel does not need the Position XY Offsets to
231 * compute a Position Value, then this field should be programmed
232 * to POSOFFSET_NONE."
234 * "SW Recommendation: If the PS kernel needs the Position Offsets
235 * to compute a Position XY value, this field should match Position
236 * ZW Interpolation Mode to ensure a consistent position.xyzw
239 * We only require XY sample offsets. So, this recommendation doesn't
240 * look useful at the moment. We might need this in future.
242 if (prog_data
->uses_pos_offset
)
243 dw6
|= GEN7_PS_POSOFFSET_SAMPLE
;
245 dw6
|= GEN7_PS_POSOFFSET_NONE
;
247 dw6
|= fast_clear_op
;
250 * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
251 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
252 * is successfully compiled. In majority of the cases that bring us
253 * better performance than 'SIMD8 only' dispatch.
255 int min_invocations_per_fragment
=
256 _mesa_get_min_invocations_per_fragment(ctx
, fp
, false);
257 assert(min_invocations_per_fragment
>= 1);
259 if (prog_data
->prog_offset_16
|| prog_data
->no_8
) {
260 dw6
|= GEN7_PS_16_DISPATCH_ENABLE
;
261 if (!prog_data
->no_8
&& min_invocations_per_fragment
== 1) {
262 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
263 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
264 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
265 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
266 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
267 ksp0
= stage_state
->prog_offset
;
268 ksp2
= stage_state
->prog_offset
+ prog_data
->prog_offset_16
;
270 dw7
|= (prog_data
->dispatch_grf_start_reg_16
<<
271 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
273 ksp0
= stage_state
->prog_offset
+ prog_data
->prog_offset_16
;
276 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
277 dw7
|= (prog_data
->base
.dispatch_grf_start_reg
<<
278 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
279 ksp0
= stage_state
->prog_offset
;
283 OUT_BATCH(_3DSTATE_PS
<< 16 | (12 - 2));
287 if (prog_data
->base
.total_scratch
) {
288 OUT_RELOC64(stage_state
->scratch_bo
,
289 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
290 ffs(prog_data
->base
.total_scratch
) - 11);
297 OUT_BATCH(0); /* kernel 1 pointer */
305 upload_ps_state(struct brw_context
*brw
)
307 /* BRW_NEW_FS_PROG_DATA */
308 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
309 gen8_upload_ps_state(brw
, brw
->fragment_program
, &brw
->wm
.base
, prog_data
,
310 brw
->wm
.fast_clear_op
);
313 const struct brw_tracked_state gen8_ps_state
= {
315 .mesa
= _NEW_MULTISAMPLE
,
316 .brw
= BRW_NEW_BATCH
|
318 BRW_NEW_FRAGMENT_PROGRAM
|
319 BRW_NEW_FS_PROG_DATA
,
321 .emit
= upload_ps_state
,