src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_wm.h"
  29 #include "intel_batchbuffer.h"
  30
  31 void
  32 gen8_upload_ps_extra(struct brw_context *brw,
  33                      const struct brw_wm_prog_data *prog_data)
  34 {
  35    struct gl_context *ctx = &brw->ctx;
  36    uint32_t dw1 = 0;
  37
  38    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  39    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  40
  41    if (prog_data->uses_kill)
  42       dw1 |= GEN8_PSX_KILL_ENABLE;
  43
  44    if (prog_data->num_varying_inputs != 0)
  45       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  46
  47    if (prog_data->uses_src_depth)
  48       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
  49
  50    if (prog_data->uses_src_w)
  51       dw1 |= GEN8_PSX_USES_SOURCE_W;
  52
  53    if (prog_data->persample_dispatch)
  54       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  55
  56    if (prog_data->uses_sample_mask) {
  57       if (brw->gen >= 9)
  58          dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
  59       else
  60          dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  61    }
  62
  63    if (prog_data->uses_omask)
  64       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  65
  66    if (brw->gen >= 9 && prog_data->pulls_bary)
  67       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  68
  69    /* The stricter cross-primitive coherency guarantees that the hardware
  70     * gives us with the "Accesses UAV" bit set for at least one shader stage
  71     * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
  72     * redundant within the current image, atomic counter and SSBO GL APIs,
  73     * which all have very loose ordering and coherency requirements and
  74     * generally rely on the application to insert explicit barriers when a
  75     * shader invocation is expected to see the memory writes performed by the
  76     * invocations of some previous primitive.  Regardless of the value of "UAV
  77     * coherency required", the "Accesses UAV" bits will implicitly cause an in
  78     * most cases useless DC flush when the lowermost stage with the bit set
  79     * finishes execution.
  80     *
  81     * It would be nice to disable it, but in some cases we can't because on
  82     * Gen8+ it also has an influence on rasterization via the PS UAV-only
  83     * signal (which could be set independently from the coherency mechanism in
  84     * the 3DSTATE_WM command on Gen7), and because in some cases it will
  85     * determine whether the hardware skips execution of the fragment shader or
  86     * not via the ThreadDispatchEnable signal.  However if we know that
  87     * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
  88     * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
  89     * difference so we may just disable it here.
  90     *
  91     * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
  92     * take into account KillPixels when no depth or stencil writes are enabled.
  93     * In order for occlusion queries to work correctly with no attachments, we
  94     * need to force-enable here.
  95     *
  96     * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
  97     */
  98    if ((_mesa_active_fragment_shader_has_side_effects(ctx) ||
  99         prog_data->uses_kill) && !brw_color_buffer_write_enabled(brw))
 100       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
 101
 102    if (prog_data->computed_stencil) {
 103       assert(brw->gen >= 9);
 104       dw1 |= GEN9_PSX_SHADER_COMPUTES_STENCIL;
 105    }
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
 109    OUT_BATCH(dw1);
 110    ADVANCE_BATCH();
 111 }
 112
 113 static void
 114 upload_ps_extra(struct brw_context *brw)
 115 {
 116    /* BRW_NEW_FS_PROG_DATA */
 117    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 118
 119    gen8_upload_ps_extra(brw, prog_data);
 120 }
 121
 122 const struct brw_tracked_state gen8_ps_extra = {
 123    .dirty = {
 124       .mesa  = _NEW_BUFFERS | _NEW_COLOR,
 125       .brw   = BRW_NEW_BLORP |
 126                BRW_NEW_CONTEXT |
 127                BRW_NEW_FS_PROG_DATA,
 128    },
 129    .emit = upload_ps_extra,
 130 };
 131
 132 static void
 133 upload_wm_state(struct brw_context *brw)
 134 {
 135    struct gl_context *ctx = &brw->ctx;
 136    uint32_t dw1 = 0;
 137
 138    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 139    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 140    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 141    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 142
 143    /* _NEW_LINE */
 144    if (ctx->Line.StippleFlag)
 145       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 146
 147    /* _NEW_POLYGON */
 148    if (ctx->Polygon.StippleFlag)
 149       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 150
 151    /* BRW_NEW_FS_PROG_DATA */
 152    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 153       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 154
 155    /* BRW_NEW_FS_PROG_DATA */
 156    if (brw->wm.prog_data->early_fragment_tests)
 157       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 158    else if (_mesa_active_fragment_shader_has_side_effects(&brw->ctx))
 159       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 160
 161    BEGIN_BATCH(2);
 162    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 163    OUT_BATCH(dw1);
 164    ADVANCE_BATCH();
 165 }
 166
 167 const struct brw_tracked_state gen8_wm_state = {
 168    .dirty = {
 169       .mesa  = _NEW_LINE |
 170                _NEW_POLYGON,
 171       .brw   = BRW_NEW_BLORP |
 172                BRW_NEW_CONTEXT |
 173                BRW_NEW_FS_PROG_DATA,
 174    },
 175    .emit = upload_wm_state,
 176 };
 177
 178 void
 179 gen8_upload_ps_state(struct brw_context *brw,
 180                      const struct brw_stage_state *stage_state,
 181                      const struct brw_wm_prog_data *prog_data,
 182                      uint32_t fast_clear_op)
 183 {
 184    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 185
 186    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 187     * incorrect for subspans where some of the pixels are unlit.  We believe
 188     * the bit just didn't take effect in previous generations.
 189     */
 190    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 191
 192    const unsigned sampler_count =
 193       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 194    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 195
 196    /* BRW_NEW_FS_PROG_DATA */
 197    dw3 |=
 198       ((prog_data->base.binding_table.size_bytes / 4) <<
 199        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 200
 201    if (prog_data->base.use_alt_mode)
 202       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 203
 204    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 205     * it implicitly scales for different GT levels (which have some # of PSDs).
 206     *
 207     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 208     */
 209    if (brw->gen >= 9)
 210       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 211    else
 212       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 213
 214    if (prog_data->base.nr_params > 0)
 215       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 216
 217    /* From the documentation for this packet:
 218     * "If the PS kernel does not need the Position XY Offsets to
 219     *  compute a Position Value, then this field should be programmed
 220     *  to POSOFFSET_NONE."
 221     *
 222     * "SW Recommendation: If the PS kernel needs the Position Offsets
 223     *  to compute a Position XY value, this field should match Position
 224     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 225     *  computation."
 226     *
 227     * We only require XY sample offsets. So, this recommendation doesn't
 228     * look useful at the moment. We might need this in future.
 229     */
 230    if (prog_data->uses_pos_offset)
 231       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 232    else
 233       dw6 |= GEN7_PS_POSOFFSET_NONE;
 234
 235    dw6 |= fast_clear_op;
 236
 237    if (prog_data->prog_offset_16 || prog_data->no_8) {
 238       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 239
 240       /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 241        * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 242        * is successfully compiled. In majority of the cases that bring us
 243        * better performance than 'SIMD8 only' dispatch.
 244        */
 245       if (!prog_data->no_8 && !prog_data->persample_dispatch) {
 246          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 247          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 248                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 249          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 250                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 251          ksp0 = stage_state->prog_offset;
 252          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 253       } else {
 254          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 255                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 256
 257          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 258       }
 259    } else {
 260       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 261       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 262               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 263       ksp0 = stage_state->prog_offset;
 264    }
 265
 266    BEGIN_BATCH(12);
 267    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 268    OUT_BATCH(ksp0);
 269    OUT_BATCH(0);
 270    OUT_BATCH(dw3);
 271    if (prog_data->base.total_scratch) {
 272       OUT_RELOC64(stage_state->scratch_bo,
 273                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 274                   ffs(prog_data->base.total_scratch) - 11);
 275    } else {
 276       OUT_BATCH(0);
 277       OUT_BATCH(0);
 278    }
 279    OUT_BATCH(dw6);
 280    OUT_BATCH(dw7);
 281    OUT_BATCH(0); /* kernel 1 pointer */
 282    OUT_BATCH(0);
 283    OUT_BATCH(ksp2);
 284    OUT_BATCH(0);
 285    ADVANCE_BATCH();
 286 }
 287
 288 static void
 289 upload_ps_state(struct brw_context *brw)
 290 {
 291    /* BRW_NEW_FS_PROG_DATA */
 292    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 293    gen8_upload_ps_state(brw, &brw->wm.base, prog_data, brw->wm.fast_clear_op);
 294 }
 295
 296 const struct brw_tracked_state gen8_ps_state = {
 297    .dirty = {
 298       .mesa  = _NEW_MULTISAMPLE,
 299       .brw   = BRW_NEW_BATCH |
 300                BRW_NEW_BLORP |
 301                BRW_NEW_FRAGMENT_PROGRAM |
 302                BRW_NEW_FS_PROG_DATA,
 303    },
 304    .emit = upload_ps_state,
 305 };