src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "intel_batchbuffer.h"
  29
  30 void
  31 gen8_upload_ps_extra(struct brw_context *brw,
  32                      const struct gl_fragment_program *fp,
  33                      const struct brw_wm_prog_data *prog_data,
  34                      bool multisampled_fbo)
  35 {
  36    struct gl_context *ctx = &brw->ctx;
  37    uint32_t dw1 = 0;
  38
  39    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  40    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  41
  42    if (prog_data->uses_kill)
  43       dw1 |= GEN8_PSX_KILL_ENABLE;
  44
  45    if (prog_data->num_varying_inputs != 0)
  46       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  47
  48    if (fp->Base.InputsRead & VARYING_BIT_POS)
  49       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  50
  51    if (multisampled_fbo &&
  52        _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
  53       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  54
  55    if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
  56       if (brw->gen >= 9)
  57          dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
  58       else
  59          dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  60    }
  61
  62    if (prog_data->uses_omask)
  63       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  64
  65    if (brw->gen >= 9 && prog_data->pulls_bary)
  66       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  67
  68    if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx) ||
  69        prog_data->base.nr_image_params)
  70       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
  74    OUT_BATCH(dw1);
  75    ADVANCE_BATCH();
  76 }
  77
  78 static void
  79 upload_ps_extra(struct brw_context *brw)
  80 {
  81    /* BRW_NEW_FRAGMENT_PROGRAM */
  82    const struct brw_fragment_program *fp =
  83       brw_fragment_program_const(brw->fragment_program);
  84    /* BRW_NEW_FS_PROG_DATA */
  85    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  86    /* BRW_NEW_NUM_SAMPLES */
  87    const bool multisampled_fbo = brw->num_samples > 1;
  88
  89    gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
  90 }
  91
  92 const struct brw_tracked_state gen8_ps_extra = {
  93    .dirty = {
  94       .mesa  = 0,
  95       .brw   = BRW_NEW_CONTEXT |
  96                BRW_NEW_FRAGMENT_PROGRAM |
  97                BRW_NEW_FS_PROG_DATA |
  98                BRW_NEW_NUM_SAMPLES,
  99    },
 100    .emit = upload_ps_extra,
 101 };
 102
 103 static void
 104 upload_wm_state(struct brw_context *brw)
 105 {
 106    struct gl_context *ctx = &brw->ctx;
 107    uint32_t dw1 = 0;
 108
 109    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 110    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 111    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 112    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 113
 114    /* _NEW_LINE */
 115    if (ctx->Line.StippleFlag)
 116       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 117
 118    /* _NEW_POLYGON */
 119    if (ctx->Polygon.StippleFlag)
 120       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 121
 122    /* BRW_NEW_FS_PROG_DATA */
 123    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 124       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 125
 126    /* BRW_NEW_FS_PROG_DATA */
 127    if (brw->wm.prog_data->early_fragment_tests)
 128       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 129    else if (brw->wm.prog_data->base.nr_image_params)
 130       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 131
 132    BEGIN_BATCH(2);
 133    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 134    OUT_BATCH(dw1);
 135    ADVANCE_BATCH();
 136 }
 137
 138 const struct brw_tracked_state gen8_wm_state = {
 139    .dirty = {
 140       .mesa  = _NEW_LINE |
 141                _NEW_POLYGON,
 142       .brw   = BRW_NEW_CONTEXT |
 143                BRW_NEW_FS_PROG_DATA,
 144    },
 145    .emit = upload_wm_state,
 146 };
 147
 148 void
 149 gen8_upload_ps_state(struct brw_context *brw,
 150                      const struct gl_fragment_program *fp,
 151                      const struct brw_stage_state *stage_state,
 152                      const struct brw_wm_prog_data *prog_data,
 153                      uint32_t fast_clear_op)
 154 {
 155    struct gl_context *ctx = &brw->ctx;
 156    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 157
 158    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 159     * incorrect for subspans where some of the pixels are unlit.  We believe
 160     * the bit just didn't take effect in previous generations.
 161     */
 162    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 163
 164    const unsigned sampler_count =
 165       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 166    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 167
 168    /* BRW_NEW_FS_PROG_DATA */
 169    dw3 |=
 170       ((prog_data->base.binding_table.size_bytes / 4) <<
 171        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 172
 173    if (prog_data->base.use_alt_mode)
 174       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 175
 176    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 177     * it implicitly scales for different GT levels (which have some # of PSDs).
 178     *
 179     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 180     */
 181    if (brw->gen >= 9)
 182       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 183    else
 184       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 185
 186    if (prog_data->base.nr_params > 0)
 187       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 188
 189    /* From the documentation for this packet:
 190     * "If the PS kernel does not need the Position XY Offsets to
 191     *  compute a Position Value, then this field should be programmed
 192     *  to POSOFFSET_NONE."
 193     *
 194     * "SW Recommendation: If the PS kernel needs the Position Offsets
 195     *  to compute a Position XY value, this field should match Position
 196     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 197     *  computation."
 198     *
 199     * We only require XY sample offsets. So, this recommendation doesn't
 200     * look useful at the moment. We might need this in future.
 201     */
 202    if (prog_data->uses_pos_offset)
 203       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 204    else
 205       dw6 |= GEN7_PS_POSOFFSET_NONE;
 206
 207    dw6 |= fast_clear_op;
 208
 209    /* _NEW_MULTISAMPLE
 210     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 211     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 212     * is successfully compiled. In majority of the cases that bring us
 213     * better performance than 'SIMD8 only' dispatch.
 214     */
 215    int min_invocations_per_fragment =
 216       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 217    assert(min_invocations_per_fragment >= 1);
 218
 219    if (prog_data->prog_offset_16 || prog_data->no_8) {
 220       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 221       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 222          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 223          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 224                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 225          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 226                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 227          ksp0 = stage_state->prog_offset;
 228          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 229       } else {
 230          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 231                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 232
 233          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 234       }
 235    } else {
 236       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 237       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 238               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 239       ksp0 = stage_state->prog_offset;
 240    }
 241
 242    BEGIN_BATCH(12);
 243    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 244    OUT_BATCH(ksp0);
 245    OUT_BATCH(0);
 246    OUT_BATCH(dw3);
 247    if (prog_data->base.total_scratch) {
 248       OUT_RELOC64(stage_state->scratch_bo,
 249                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 250                   ffs(prog_data->base.total_scratch) - 11);
 251    } else {
 252       OUT_BATCH(0);
 253       OUT_BATCH(0);
 254    }
 255    OUT_BATCH(dw6);
 256    OUT_BATCH(dw7);
 257    OUT_BATCH(0); /* kernel 1 pointer */
 258    OUT_BATCH(0);
 259    OUT_BATCH(ksp2);
 260    OUT_BATCH(0);
 261    ADVANCE_BATCH();
 262 }
 263
 264 static void
 265 upload_ps_state(struct brw_context *brw)
 266 {
 267    /* BRW_NEW_FS_PROG_DATA */
 268    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 269    gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 270                         brw->wm.fast_clear_op);
 271 }
 272
 273 const struct brw_tracked_state gen8_ps_state = {
 274    .dirty = {
 275       .mesa  = _NEW_MULTISAMPLE,
 276       .brw   = BRW_NEW_BATCH |
 277                BRW_NEW_FRAGMENT_PROGRAM |
 278                BRW_NEW_FS_PROG_DATA,
 279    },
 280    .emit = upload_ps_state,
 281 };