i965: Add missing sample shading bits to Gen8's 3DSTATE_PS_EXTRA.
[mesa.git] / src / mesa / drivers / dri / i965 / gen8_ps_state.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdbool.h>
25 #include "program/program.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
28 #include "intel_batchbuffer.h"
29
30 static void
31 upload_ps_extra(struct brw_context *brw)
32 {
33 struct gl_context *ctx = &brw->ctx;
34 /* BRW_NEW_FRAGMENT_PROGRAM */
35 const struct brw_fragment_program *fp =
36 brw_fragment_program_const(brw->fragment_program);
37 uint32_t dw1 = 0;
38
39 dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
40
41 if (fp->program.UsesKill)
42 dw1 |= GEN8_PSX_KILL_ENABLE;
43
44 /* BRW_NEW_FRAGMENT_PROGRAM */
45 if (brw->wm.prog_data->num_varying_inputs != 0)
46 dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
47
48 if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
49 switch (fp->program.FragDepthLayout) {
50 case FRAG_DEPTH_LAYOUT_NONE:
51 case FRAG_DEPTH_LAYOUT_ANY:
52 dw1 |= GEN8_PSX_PSCDEPTH_ON;
53 break;
54 case FRAG_DEPTH_LAYOUT_GREATER:
55 dw1 |= GEN8_PSX_PSCDEPTH_ON_GE;
56 break;
57 case FRAG_DEPTH_LAYOUT_LESS:
58 dw1 |= GEN8_PSX_PSCDEPTH_ON_LE;
59 break;
60 case FRAG_DEPTH_LAYOUT_UNCHANGED:
61 break;
62 }
63 }
64
65 if (fp->program.Base.InputsRead & VARYING_BIT_POS)
66 dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
67
68 /* _NEW_BUFFERS | _NEW_MULTISAMPLE */
69 bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
70 if (multisampled_fbo &&
71 _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1)
72 dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
73
74 if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
75 dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
76
77 if (brw->wm.prog_data->uses_omask)
78 dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
79
80 BEGIN_BATCH(2);
81 OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
82 OUT_BATCH(dw1);
83 ADVANCE_BATCH();
84 }
85
86 const struct brw_tracked_state gen8_ps_extra = {
87 .dirty = {
88 .mesa = _NEW_BUFFERS | _NEW_MULTISAMPLE,
89 .brw = BRW_NEW_CONTEXT | BRW_NEW_FRAGMENT_PROGRAM,
90 .cache = 0,
91 },
92 .emit = upload_ps_extra,
93 };
94
95 static void
96 upload_wm_state(struct brw_context *brw)
97 {
98 struct gl_context *ctx = &brw->ctx;
99 uint32_t dw1 = 0;
100
101 dw1 |= GEN7_WM_STATISTICS_ENABLE;
102 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
103 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
104 dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
105
106 /* _NEW_LINE */
107 if (ctx->Line.StippleFlag)
108 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
109
110 /* _NEW_POLYGON */
111 if (ctx->Polygon.StippleFlag)
112 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
113
114 /* CACHE_NEW_WM_PROG */
115 dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
116 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
117
118 BEGIN_BATCH(2);
119 OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
120 OUT_BATCH(dw1);
121 ADVANCE_BATCH();
122 }
123
124 const struct brw_tracked_state gen8_wm_state = {
125 .dirty = {
126 .mesa = _NEW_LINE | _NEW_POLYGON,
127 .brw = BRW_NEW_CONTEXT,
128 .cache = CACHE_NEW_WM_PROG,
129 },
130 .emit = upload_wm_state,
131 };
132
133 static void
134 upload_ps_state(struct brw_context *brw)
135 {
136 struct gl_context *ctx = &brw->ctx;
137 uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
138
139 /* BRW_NEW_PS_BINDING_TABLE */
140 BEGIN_BATCH(2);
141 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
142 OUT_BATCH(brw->wm.base.bind_bo_offset);
143 ADVANCE_BATCH();
144
145 /* CACHE_NEW_SAMPLER */
146 BEGIN_BATCH(2);
147 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
148 OUT_BATCH(brw->wm.base.sampler_offset);
149 ADVANCE_BATCH();
150
151 /* CACHE_NEW_WM_PROG */
152 gen8_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
153
154 /* Initialize the execution mask with VMask. Otherwise, derivatives are
155 * incorrect for subspans where some of the pixels are unlit. We believe
156 * the bit just didn't take effect in previous generations.
157 */
158 dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
159
160 /* CACHE_NEW_SAMPLER */
161 dw3 |=
162 (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
163
164 /* CACHE_NEW_WM_PROG */
165 dw3 |=
166 ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
167 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
168
169 /* Use ALT floating point mode for ARB fragment programs, because they
170 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
171 * rendering, CurrentFragmentProgram is used for this check to
172 * differentiate between the GLSL and non-GLSL cases.
173 */
174 if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
175 dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
176
177 dw6 |= (brw->max_wm_threads - 2) << HSW_PS_MAX_THREADS_SHIFT;
178
179 /* CACHE_NEW_WM_PROG */
180 if (brw->wm.prog_data->base.nr_params > 0)
181 dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
182
183 dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
184 if (brw->wm.prog_data->prog_offset_16)
185 dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
186
187 dw7 |=
188 brw->wm.prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0 |
189 brw->wm.prog_data->first_curbe_grf_16<< GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
190
191 BEGIN_BATCH(12);
192 OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
193 OUT_BATCH(brw->wm.base.prog_offset);
194 OUT_BATCH(0);
195 OUT_BATCH(dw3);
196 if (brw->wm.prog_data->total_scratch) {
197 OUT_RELOC64(brw->wm.base.scratch_bo,
198 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
199 ffs(brw->wm.prog_data->total_scratch) - 11);
200 } else {
201 OUT_BATCH(0);
202 OUT_BATCH(0);
203 }
204 OUT_BATCH(dw6);
205 OUT_BATCH(dw7);
206 OUT_BATCH(0); /* kernel 1 pointer */
207 OUT_BATCH(0);
208 OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
209 OUT_BATCH(0);
210 ADVANCE_BATCH();
211 }
212
213 const struct brw_tracked_state gen8_ps_state = {
214 .dirty = {
215 .mesa = _NEW_PROGRAM_CONSTANTS,
216 .brw = BRW_NEW_FRAGMENT_PROGRAM |
217 BRW_NEW_PS_BINDING_TABLE |
218 BRW_NEW_BATCH |
219 BRW_NEW_PUSH_CONSTANT_ALLOCATION,
220 .cache = CACHE_NEW_SAMPLER | CACHE_NEW_WM_PROG
221 },
222 .emit = upload_ps_state,
223 };