2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "program/program.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
28 #include "intel_batchbuffer.h"
31 upload_ps_extra(struct brw_context
*brw
)
33 struct gl_context
*ctx
= &brw
->ctx
;
34 /* BRW_NEW_FRAGMENT_PROGRAM */
35 const struct brw_fragment_program
*fp
=
36 brw_fragment_program_const(brw
->fragment_program
);
39 dw1
|= GEN8_PSX_PIXEL_SHADER_VALID
;
41 if (fp
->program
.UsesKill
)
42 dw1
|= GEN8_PSX_KILL_ENABLE
;
44 /* BRW_NEW_FRAGMENT_PROGRAM */
45 if (brw
->wm
.prog_data
->num_varying_inputs
!= 0)
46 dw1
|= GEN8_PSX_ATTRIBUTE_ENABLE
;
48 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
49 switch (fp
->program
.FragDepthLayout
) {
50 case FRAG_DEPTH_LAYOUT_NONE
:
51 case FRAG_DEPTH_LAYOUT_ANY
:
52 dw1
|= GEN8_PSX_PSCDEPTH_ON
;
54 case FRAG_DEPTH_LAYOUT_GREATER
:
55 dw1
|= GEN8_PSX_PSCDEPTH_ON_GE
;
57 case FRAG_DEPTH_LAYOUT_LESS
:
58 dw1
|= GEN8_PSX_PSCDEPTH_ON_LE
;
60 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
65 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
66 dw1
|= GEN8_PSX_USES_SOURCE_DEPTH
| GEN8_PSX_USES_SOURCE_W
;
68 /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
69 bool multisampled_fbo
= brw
->num_samples
> 1;
70 if (multisampled_fbo
&&
71 _mesa_get_min_invocations_per_fragment(ctx
, &fp
->program
, false) > 1)
72 dw1
|= GEN8_PSX_SHADER_IS_PER_SAMPLE
;
74 if (fp
->program
.Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
)
75 dw1
|= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK
;
77 if (brw
->wm
.prog_data
->uses_omask
)
78 dw1
|= GEN8_PSX_OMASK_TO_RENDER_TARGET
;
81 OUT_BATCH(_3DSTATE_PS_EXTRA
<< 16 | (2 - 2));
86 const struct brw_tracked_state gen8_ps_extra
= {
88 .mesa
= _NEW_MULTISAMPLE
,
89 .brw
= BRW_NEW_CONTEXT
| BRW_NEW_FRAGMENT_PROGRAM
| BRW_NEW_NUM_SAMPLES
,
92 .emit
= upload_ps_extra
,
96 upload_wm_state(struct brw_context
*brw
)
98 struct gl_context
*ctx
= &brw
->ctx
;
101 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
102 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
103 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
104 dw1
|= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT
;
107 if (ctx
->Line
.StippleFlag
)
108 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
111 if (ctx
->Polygon
.StippleFlag
)
112 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
114 /* CACHE_NEW_WM_PROG */
115 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
116 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
119 OUT_BATCH(_3DSTATE_WM
<< 16 | (2 - 2));
124 const struct brw_tracked_state gen8_wm_state
= {
126 .mesa
= _NEW_LINE
| _NEW_POLYGON
,
127 .brw
= BRW_NEW_CONTEXT
,
128 .cache
= CACHE_NEW_WM_PROG
,
130 .emit
= upload_wm_state
,
134 upload_ps_state(struct brw_context
*brw
)
136 struct gl_context
*ctx
= &brw
->ctx
;
137 uint32_t dw3
= 0, dw6
= 0, dw7
= 0, ksp0
, ksp2
= 0;
139 /* Initialize the execution mask with VMask. Otherwise, derivatives are
140 * incorrect for subspans where some of the pixels are unlit. We believe
141 * the bit just didn't take effect in previous generations.
143 dw3
|= GEN7_PS_VECTOR_MASK_ENABLE
;
146 (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
148 /* CACHE_NEW_WM_PROG */
150 ((brw
->wm
.prog_data
->base
.binding_table
.size_bytes
/ 4) <<
151 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
153 /* Use ALT floating point mode for ARB fragment programs, because they
154 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
155 * rendering, CurrentFragmentProgram is used for this check to
156 * differentiate between the GLSL and non-GLSL cases.
158 if (ctx
->Shader
.CurrentProgram
[MESA_SHADER_FRAGMENT
] == NULL
)
159 dw3
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
161 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
162 * it implicitly scales for different GT levels (which have some # of PSDs).
164 dw6
|= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT
;
166 /* CACHE_NEW_WM_PROG */
167 if (brw
->wm
.prog_data
->base
.nr_params
> 0)
168 dw6
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
170 /* From the documentation for this packet:
171 * "If the PS kernel does not need the Position XY Offsets to
172 * compute a Position Value, then this field should be programmed
173 * to POSOFFSET_NONE."
175 * "SW Recommendation: If the PS kernel needs the Position Offsets
176 * to compute a Position XY value, this field should match Position
177 * ZW Interpolation Mode to ensure a consistent position.xyzw
180 * We only require XY sample offsets. So, this recommendation doesn't
181 * look useful at the moment. We might need this in future.
183 if (brw
->wm
.prog_data
->uses_pos_offset
)
184 dw6
|= GEN7_PS_POSOFFSET_SAMPLE
;
186 dw6
|= GEN7_PS_POSOFFSET_NONE
;
189 * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
190 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
191 * is successfully compiled. In majority of the cases that bring us
192 * better performance than 'SIMD8 only' dispatch.
194 int min_invocations_per_fragment
=
195 _mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false);
196 assert(min_invocations_per_fragment
>= 1);
198 if (brw
->wm
.prog_data
->prog_offset_16
) {
199 dw6
|= GEN7_PS_16_DISPATCH_ENABLE
;
200 if (min_invocations_per_fragment
== 1) {
201 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
202 dw7
|= (brw
->wm
.prog_data
->base
.dispatch_grf_start_reg
<<
203 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
204 dw7
|= (brw
->wm
.prog_data
->dispatch_grf_start_reg_16
<<
205 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
206 ksp0
= brw
->wm
.base
.prog_offset
;
207 ksp2
= brw
->wm
.base
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
;
209 dw7
|= (brw
->wm
.prog_data
->dispatch_grf_start_reg_16
<<
210 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
212 ksp0
= brw
->wm
.base
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
;
215 dw6
|= GEN7_PS_8_DISPATCH_ENABLE
;
216 dw7
|= (brw
->wm
.prog_data
->base
.dispatch_grf_start_reg
<<
217 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
218 ksp0
= brw
->wm
.base
.prog_offset
;
222 OUT_BATCH(_3DSTATE_PS
<< 16 | (12 - 2));
226 if (brw
->wm
.prog_data
->total_scratch
) {
227 OUT_RELOC64(brw
->wm
.base
.scratch_bo
,
228 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
229 ffs(brw
->wm
.prog_data
->total_scratch
) - 11);
236 OUT_BATCH(0); /* kernel 1 pointer */
243 const struct brw_tracked_state gen8_ps_state
= {
245 .mesa
= _NEW_MULTISAMPLE
,
246 .brw
= BRW_NEW_FRAGMENT_PROGRAM
|
248 .cache
= CACHE_NEW_WM_PROG
250 .emit
= upload_ps_state
,