src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_wm.h"
  29 #include "intel_batchbuffer.h"
  30
  31 void
  32 gen8_upload_ps_extra(struct brw_context *brw,
  33                      const struct gl_fragment_program *fp,
  34                      const struct brw_wm_prog_data *prog_data,
  35                      bool multisampled_fbo)
  36 {
  37    struct gl_context *ctx = &brw->ctx;
  38    uint32_t dw1 = 0;
  39
  40    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  41    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  42
  43    if (prog_data->uses_kill)
  44       dw1 |= GEN8_PSX_KILL_ENABLE;
  45
  46    if (prog_data->num_varying_inputs != 0)
  47       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  48
  49    if (fp->Base.InputsRead & VARYING_BIT_POS)
  50       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  51
  52    if (multisampled_fbo &&
  53        _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
  54       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  55
  56    if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
  57       if (brw->gen >= 9)
  58          dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
  59       else
  60          dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  61    }
  62
  63    if (prog_data->uses_omask)
  64       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  65
  66    if (brw->gen >= 9 && prog_data->pulls_bary)
  67       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  68
  69    /* The stricter cross-primitive coherency guarantees that the hardware
  70     * gives us with the "Accesses UAV" bit set for at least one shader stage
  71     * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
  72     * redundant within the current image, atomic counter and SSBO GL APIs,
  73     * which all have very loose ordering and coherency requirements and
  74     * generally rely on the application to insert explicit barriers when a
  75     * shader invocation is expected to see the memory writes performed by the
  76     * invocations of some previous primitive.  Regardless of the value of "UAV
  77     * coherency required", the "Accesses UAV" bits will implicitly cause an in
  78     * most cases useless DC flush when the lowermost stage with the bit set
  79     * finishes execution.
  80     *
  81     * It would be nice to disable it, but in some cases we can't because on
  82     * Gen8+ it also has an influence on rasterization via the PS UAV-only
  83     * signal (which could be set independently from the coherency mechanism in
  84     * the 3DSTATE_WM command on Gen7), and because in some cases it will
  85     * determine whether the hardware skips execution of the fragment shader or
  86     * not via the ThreadDispatchEnable signal.  However if we know that
  87     * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
  88     * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
  89     * difference so we may just disable it here.
  90     *
  91     * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
  92     */
  93    if ((_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx) ||
  94         prog_data->base.nr_image_params) &&
  95        !brw_color_buffer_write_enabled(brw))
  96       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
  97
  98    BEGIN_BATCH(2);
  99    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
 100    OUT_BATCH(dw1);
 101    ADVANCE_BATCH();
 102 }
 103
 104 static void
 105 upload_ps_extra(struct brw_context *brw)
 106 {
 107    /* BRW_NEW_FRAGMENT_PROGRAM */
 108    const struct brw_fragment_program *fp =
 109       brw_fragment_program_const(brw->fragment_program);
 110    /* BRW_NEW_FS_PROG_DATA */
 111    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 112    /* BRW_NEW_NUM_SAMPLES */
 113    const bool multisampled_fbo = brw->num_samples > 1;
 114
 115    gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
 116 }
 117
 118 const struct brw_tracked_state gen8_ps_extra = {
 119    .dirty = {
 120       .mesa  = _NEW_BUFFERS | _NEW_COLOR,
 121       .brw   = BRW_NEW_CONTEXT |
 122                BRW_NEW_FRAGMENT_PROGRAM |
 123                BRW_NEW_FS_PROG_DATA |
 124                BRW_NEW_NUM_SAMPLES,
 125    },
 126    .emit = upload_ps_extra,
 127 };
 128
 129 static void
 130 upload_wm_state(struct brw_context *brw)
 131 {
 132    struct gl_context *ctx = &brw->ctx;
 133    uint32_t dw1 = 0;
 134
 135    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 136    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 137    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 138    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 139
 140    /* _NEW_LINE */
 141    if (ctx->Line.StippleFlag)
 142       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 143
 144    /* _NEW_POLYGON */
 145    if (ctx->Polygon.StippleFlag)
 146       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 147
 148    /* BRW_NEW_FS_PROG_DATA */
 149    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 150       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 151
 152    /* BRW_NEW_FS_PROG_DATA */
 153    if (brw->wm.prog_data->early_fragment_tests)
 154       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 155    else if (brw->wm.prog_data->base.nr_image_params)
 156       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 157
 158    BEGIN_BATCH(2);
 159    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 160    OUT_BATCH(dw1);
 161    ADVANCE_BATCH();
 162 }
 163
 164 const struct brw_tracked_state gen8_wm_state = {
 165    .dirty = {
 166       .mesa  = _NEW_LINE |
 167                _NEW_POLYGON,
 168       .brw   = BRW_NEW_CONTEXT |
 169                BRW_NEW_FS_PROG_DATA,
 170    },
 171    .emit = upload_wm_state,
 172 };
 173
 174 void
 175 gen8_upload_ps_state(struct brw_context *brw,
 176                      const struct gl_fragment_program *fp,
 177                      const struct brw_stage_state *stage_state,
 178                      const struct brw_wm_prog_data *prog_data,
 179                      uint32_t fast_clear_op)
 180 {
 181    struct gl_context *ctx = &brw->ctx;
 182    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 183
 184    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 185     * incorrect for subspans where some of the pixels are unlit.  We believe
 186     * the bit just didn't take effect in previous generations.
 187     */
 188    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 189
 190    const unsigned sampler_count =
 191       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 192    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 193
 194    /* BRW_NEW_FS_PROG_DATA */
 195    dw3 |=
 196       ((prog_data->base.binding_table.size_bytes / 4) <<
 197        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 198
 199    if (prog_data->base.use_alt_mode)
 200       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 201
 202    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 203     * it implicitly scales for different GT levels (which have some # of PSDs).
 204     *
 205     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 206     */
 207    if (brw->gen >= 9)
 208       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 209    else
 210       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 211
 212    if (prog_data->base.nr_params > 0)
 213       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 214
 215    /* From the documentation for this packet:
 216     * "If the PS kernel does not need the Position XY Offsets to
 217     *  compute a Position Value, then this field should be programmed
 218     *  to POSOFFSET_NONE."
 219     *
 220     * "SW Recommendation: If the PS kernel needs the Position Offsets
 221     *  to compute a Position XY value, this field should match Position
 222     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 223     *  computation."
 224     *
 225     * We only require XY sample offsets. So, this recommendation doesn't
 226     * look useful at the moment. We might need this in future.
 227     */
 228    if (prog_data->uses_pos_offset)
 229       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 230    else
 231       dw6 |= GEN7_PS_POSOFFSET_NONE;
 232
 233    dw6 |= fast_clear_op;
 234
 235    /* _NEW_MULTISAMPLE
 236     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 237     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 238     * is successfully compiled. In majority of the cases that bring us
 239     * better performance than 'SIMD8 only' dispatch.
 240     */
 241    int min_invocations_per_fragment =
 242       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 243    assert(min_invocations_per_fragment >= 1);
 244
 245    if (prog_data->prog_offset_16 || prog_data->no_8) {
 246       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 247       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 248          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 249          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 250                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 251          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 252                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 253          ksp0 = stage_state->prog_offset;
 254          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 255       } else {
 256          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 257                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 258
 259          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 260       }
 261    } else {
 262       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 263       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 264               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 265       ksp0 = stage_state->prog_offset;
 266    }
 267
 268    BEGIN_BATCH(12);
 269    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 270    OUT_BATCH(ksp0);
 271    OUT_BATCH(0);
 272    OUT_BATCH(dw3);
 273    if (prog_data->base.total_scratch) {
 274       OUT_RELOC64(stage_state->scratch_bo,
 275                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 276                   ffs(prog_data->base.total_scratch) - 11);
 277    } else {
 278       OUT_BATCH(0);
 279       OUT_BATCH(0);
 280    }
 281    OUT_BATCH(dw6);
 282    OUT_BATCH(dw7);
 283    OUT_BATCH(0); /* kernel 1 pointer */
 284    OUT_BATCH(0);
 285    OUT_BATCH(ksp2);
 286    OUT_BATCH(0);
 287    ADVANCE_BATCH();
 288 }
 289
 290 static void
 291 upload_ps_state(struct brw_context *brw)
 292 {
 293    /* BRW_NEW_FS_PROG_DATA */
 294    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 295    gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 296                         brw->wm.fast_clear_op);
 297 }
 298
 299 const struct brw_tracked_state gen8_ps_state = {
 300    .dirty = {
 301       .mesa  = _NEW_MULTISAMPLE,
 302       .brw   = BRW_NEW_BATCH |
 303                BRW_NEW_FRAGMENT_PROGRAM |
 304                BRW_NEW_FS_PROG_DATA,
 305    },
 306    .emit = upload_ps_state,
 307 };