src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "intel_batchbuffer.h"
  29
  30 void
  31 gen8_upload_ps_extra(struct brw_context *brw,
  32                      const struct gl_fragment_program *fp,
  33                      const struct brw_wm_prog_data *prog_data,
  34                      bool multisampled_fbo)
  35 {
  36    struct gl_context *ctx = &brw->ctx;
  37    uint32_t dw1 = 0;
  38
  39    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  40    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  41
  42    if (prog_data->uses_kill)
  43       dw1 |= GEN8_PSX_KILL_ENABLE;
  44
  45    if (prog_data->num_varying_inputs != 0)
  46       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  47
  48    if (fp->Base.InputsRead & VARYING_BIT_POS)
  49       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  50
  51    if (multisampled_fbo &&
  52        _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
  53       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  54
  55    if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
  56       dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  57
  58    if (prog_data->uses_omask)
  59       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  60
  61    if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx))
  62       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
  63
  64    BEGIN_BATCH(2);
  65    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
  66    OUT_BATCH(dw1);
  67    ADVANCE_BATCH();
  68 }
  69
  70 static void
  71 upload_ps_extra(struct brw_context *brw)
  72 {
  73    /* BRW_NEW_FRAGMENT_PROGRAM */
  74    const struct brw_fragment_program *fp =
  75       brw_fragment_program_const(brw->fragment_program);
  76    /* BRW_NEW_FS_PROG_DATA */
  77    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  78    /* BRW_NEW_NUM_SAMPLES */
  79    const bool multisampled_fbo = brw->num_samples > 1;
  80
  81    gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
  82 }
  83
  84 const struct brw_tracked_state gen8_ps_extra = {
  85    .dirty = {
  86       .mesa  = 0,
  87       .brw   = BRW_NEW_CONTEXT |
  88                BRW_NEW_FRAGMENT_PROGRAM |
  89                BRW_NEW_FS_PROG_DATA |
  90                BRW_NEW_NUM_SAMPLES,
  91    },
  92    .emit = upload_ps_extra,
  93 };
  94
  95 static void
  96 upload_wm_state(struct brw_context *brw)
  97 {
  98    struct gl_context *ctx = &brw->ctx;
  99    uint32_t dw1 = 0;
 100
 101    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 102    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 103    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 104    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 105
 106    /* _NEW_LINE */
 107    if (ctx->Line.StippleFlag)
 108       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 109
 110    /* _NEW_POLYGON */
 111    if (ctx->Polygon.StippleFlag)
 112       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 113
 114    /* BRW_NEW_FS_PROG_DATA */
 115    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 116       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 117
 118    BEGIN_BATCH(2);
 119    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 120    OUT_BATCH(dw1);
 121    ADVANCE_BATCH();
 122 }
 123
 124 const struct brw_tracked_state gen8_wm_state = {
 125    .dirty = {
 126       .mesa  = _NEW_LINE |
 127                _NEW_POLYGON,
 128       .brw   = BRW_NEW_CONTEXT |
 129                BRW_NEW_FS_PROG_DATA,
 130    },
 131    .emit = upload_wm_state,
 132 };
 133
 134 void
 135 gen8_upload_ps_state(struct brw_context *brw,
 136                      const struct gl_fragment_program *fp,
 137                      const struct brw_stage_state *stage_state,
 138                      const struct brw_wm_prog_data *prog_data,
 139                      uint32_t fast_clear_op)
 140 {
 141    struct gl_context *ctx = &brw->ctx;
 142    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 143
 144    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 145     * incorrect for subspans where some of the pixels are unlit.  We believe
 146     * the bit just didn't take effect in previous generations.
 147     */
 148    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 149
 150    const unsigned sampler_count =
 151       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 152    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 153
 154    /* BRW_NEW_FS_PROG_DATA */
 155    dw3 |=
 156       ((prog_data->base.binding_table.size_bytes / 4) <<
 157        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 158
 159    if (prog_data->base.use_alt_mode)
 160       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 161
 162    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 163     * it implicitly scales for different GT levels (which have some # of PSDs).
 164     *
 165     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 166     */
 167    if (brw->gen >= 9)
 168       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 169    else
 170       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 171
 172    if (prog_data->base.nr_params > 0)
 173       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 174
 175    /* From the documentation for this packet:
 176     * "If the PS kernel does not need the Position XY Offsets to
 177     *  compute a Position Value, then this field should be programmed
 178     *  to POSOFFSET_NONE."
 179     *
 180     * "SW Recommendation: If the PS kernel needs the Position Offsets
 181     *  to compute a Position XY value, this field should match Position
 182     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 183     *  computation."
 184     *
 185     * We only require XY sample offsets. So, this recommendation doesn't
 186     * look useful at the moment. We might need this in future.
 187     */
 188    if (prog_data->uses_pos_offset)
 189       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 190    else
 191       dw6 |= GEN7_PS_POSOFFSET_NONE;
 192
 193    dw6 |= fast_clear_op;
 194
 195    /* _NEW_MULTISAMPLE
 196     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 197     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 198     * is successfully compiled. In majority of the cases that bring us
 199     * better performance than 'SIMD8 only' dispatch.
 200     */
 201    int min_invocations_per_fragment =
 202       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 203    assert(min_invocations_per_fragment >= 1);
 204
 205    if (prog_data->prog_offset_16 || prog_data->no_8) {
 206       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 207       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 208          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 209          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 210                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 211          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 212                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 213          ksp0 = stage_state->prog_offset;
 214          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 215       } else {
 216          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 217                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 218
 219          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 220       }
 221    } else {
 222       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 223       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 224               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 225       ksp0 = stage_state->prog_offset;
 226    }
 227
 228    BEGIN_BATCH(12);
 229    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 230    OUT_BATCH(ksp0);
 231    OUT_BATCH(0);
 232    OUT_BATCH(dw3);
 233    if (prog_data->base.total_scratch) {
 234       OUT_RELOC64(stage_state->scratch_bo,
 235                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 236                   ffs(prog_data->base.total_scratch) - 11);
 237    } else {
 238       OUT_BATCH(0);
 239       OUT_BATCH(0);
 240    }
 241    OUT_BATCH(dw6);
 242    OUT_BATCH(dw7);
 243    OUT_BATCH(0); /* kernel 1 pointer */
 244    OUT_BATCH(0);
 245    OUT_BATCH(ksp2);
 246    OUT_BATCH(0);
 247    ADVANCE_BATCH();
 248 }
 249
 250 static void
 251 upload_ps_state(struct brw_context *brw)
 252 {
 253    /* BRW_NEW_FS_PROG_DATA */
 254    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 255    gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 256                         brw->wm.fast_clear_op);
 257 }
 258
 259 const struct brw_tracked_state gen8_ps_state = {
 260    .dirty = {
 261       .mesa  = _NEW_MULTISAMPLE,
 262       .brw   = BRW_NEW_BATCH |
 263                BRW_NEW_FRAGMENT_PROGRAM |
 264                BRW_NEW_FS_PROG_DATA,
 265    },
 266    .emit = upload_ps_state,
 267 };