src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "intel_batchbuffer.h"
  29
  30 void
  31 gen8_upload_ps_extra(struct brw_context *brw,
  32                      const struct gl_fragment_program *fp,
  33                      const struct brw_wm_prog_data *prog_data,
  34                      bool multisampled_fbo)
  35 {
  36    struct gl_context *ctx = &brw->ctx;
  37    uint32_t dw1 = 0;
  38
  39    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  40    dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
  41
  42    if (prog_data->uses_kill)
  43       dw1 |= GEN8_PSX_KILL_ENABLE;
  44
  45    if (prog_data->num_varying_inputs != 0)
  46       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  47
  48    if (fp->Base.InputsRead & VARYING_BIT_POS)
  49       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  50
  51    if (multisampled_fbo &&
  52        _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
  53       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  54
  55    if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
  56       dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  57
  58    if (prog_data->uses_omask)
  59       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  60
  61    if (brw->gen >= 9 && prog_data->pulls_bary)
  62       dw1 |= GEN9_PSX_SHADER_PULLS_BARY;
  63
  64    if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx) ||
  65        prog_data->base.nr_image_params)
  66       dw1 |= GEN8_PSX_SHADER_HAS_UAV;
  67
  68    BEGIN_BATCH(2);
  69    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
  70    OUT_BATCH(dw1);
  71    ADVANCE_BATCH();
  72 }
  73
  74 static void
  75 upload_ps_extra(struct brw_context *brw)
  76 {
  77    /* BRW_NEW_FRAGMENT_PROGRAM */
  78    const struct brw_fragment_program *fp =
  79       brw_fragment_program_const(brw->fragment_program);
  80    /* BRW_NEW_FS_PROG_DATA */
  81    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  82    /* BRW_NEW_NUM_SAMPLES */
  83    const bool multisampled_fbo = brw->num_samples > 1;
  84
  85    gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
  86 }
  87
  88 const struct brw_tracked_state gen8_ps_extra = {
  89    .dirty = {
  90       .mesa  = 0,
  91       .brw   = BRW_NEW_CONTEXT |
  92                BRW_NEW_FRAGMENT_PROGRAM |
  93                BRW_NEW_FS_PROG_DATA |
  94                BRW_NEW_NUM_SAMPLES,
  95    },
  96    .emit = upload_ps_extra,
  97 };
  98
  99 static void
 100 upload_wm_state(struct brw_context *brw)
 101 {
 102    struct gl_context *ctx = &brw->ctx;
 103    uint32_t dw1 = 0;
 104
 105    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 106    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 107    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 108    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 109
 110    /* _NEW_LINE */
 111    if (ctx->Line.StippleFlag)
 112       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 113
 114    /* _NEW_POLYGON */
 115    if (ctx->Polygon.StippleFlag)
 116       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 117
 118    /* BRW_NEW_FS_PROG_DATA */
 119    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 120       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 121
 122    BEGIN_BATCH(2);
 123    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 124    OUT_BATCH(dw1);
 125    ADVANCE_BATCH();
 126 }
 127
 128 const struct brw_tracked_state gen8_wm_state = {
 129    .dirty = {
 130       .mesa  = _NEW_LINE |
 131                _NEW_POLYGON,
 132       .brw   = BRW_NEW_CONTEXT |
 133                BRW_NEW_FS_PROG_DATA,
 134    },
 135    .emit = upload_wm_state,
 136 };
 137
 138 void
 139 gen8_upload_ps_state(struct brw_context *brw,
 140                      const struct gl_fragment_program *fp,
 141                      const struct brw_stage_state *stage_state,
 142                      const struct brw_wm_prog_data *prog_data,
 143                      uint32_t fast_clear_op)
 144 {
 145    struct gl_context *ctx = &brw->ctx;
 146    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 147
 148    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 149     * incorrect for subspans where some of the pixels are unlit.  We believe
 150     * the bit just didn't take effect in previous generations.
 151     */
 152    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 153
 154    const unsigned sampler_count =
 155       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 156    dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 157
 158    /* BRW_NEW_FS_PROG_DATA */
 159    dw3 |=
 160       ((prog_data->base.binding_table.size_bytes / 4) <<
 161        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 162
 163    if (prog_data->base.use_alt_mode)
 164       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 165
 166    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 167     * it implicitly scales for different GT levels (which have some # of PSDs).
 168     *
 169     * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
 170     */
 171    if (brw->gen >= 9)
 172       dw6 |= (64 - 1) << HSW_PS_MAX_THREADS_SHIFT;
 173    else
 174       dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 175
 176    if (prog_data->base.nr_params > 0)
 177       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 178
 179    /* From the documentation for this packet:
 180     * "If the PS kernel does not need the Position XY Offsets to
 181     *  compute a Position Value, then this field should be programmed
 182     *  to POSOFFSET_NONE."
 183     *
 184     * "SW Recommendation: If the PS kernel needs the Position Offsets
 185     *  to compute a Position XY value, this field should match Position
 186     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 187     *  computation."
 188     *
 189     * We only require XY sample offsets. So, this recommendation doesn't
 190     * look useful at the moment. We might need this in future.
 191     */
 192    if (prog_data->uses_pos_offset)
 193       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 194    else
 195       dw6 |= GEN7_PS_POSOFFSET_NONE;
 196
 197    dw6 |= fast_clear_op;
 198
 199    /* _NEW_MULTISAMPLE
 200     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 201     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 202     * is successfully compiled. In majority of the cases that bring us
 203     * better performance than 'SIMD8 only' dispatch.
 204     */
 205    int min_invocations_per_fragment =
 206       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 207    assert(min_invocations_per_fragment >= 1);
 208
 209    if (prog_data->prog_offset_16 || prog_data->no_8) {
 210       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 211       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 212          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 213          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 214                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 215          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 216                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 217          ksp0 = stage_state->prog_offset;
 218          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 219       } else {
 220          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 221                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 222
 223          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 224       }
 225    } else {
 226       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 227       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 228               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 229       ksp0 = stage_state->prog_offset;
 230    }
 231
 232    BEGIN_BATCH(12);
 233    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 234    OUT_BATCH(ksp0);
 235    OUT_BATCH(0);
 236    OUT_BATCH(dw3);
 237    if (prog_data->base.total_scratch) {
 238       OUT_RELOC64(stage_state->scratch_bo,
 239                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 240                   ffs(prog_data->base.total_scratch) - 11);
 241    } else {
 242       OUT_BATCH(0);
 243       OUT_BATCH(0);
 244    }
 245    OUT_BATCH(dw6);
 246    OUT_BATCH(dw7);
 247    OUT_BATCH(0); /* kernel 1 pointer */
 248    OUT_BATCH(0);
 249    OUT_BATCH(ksp2);
 250    OUT_BATCH(0);
 251    ADVANCE_BATCH();
 252 }
 253
 254 static void
 255 upload_ps_state(struct brw_context *brw)
 256 {
 257    /* BRW_NEW_FS_PROG_DATA */
 258    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 259    gen8_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 260                         brw->wm.fast_clear_op);
 261 }
 262
 263 const struct brw_tracked_state gen8_ps_state = {
 264    .dirty = {
 265       .mesa  = _NEW_MULTISAMPLE,
 266       .brw   = BRW_NEW_BATCH |
 267                BRW_NEW_FRAGMENT_PROGRAM |
 268                BRW_NEW_FS_PROG_DATA,
 269    },
 270    .emit = upload_ps_state,
 271 };