src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "program/program.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "intel_batchbuffer.h"
  29
  30 static void
  31 upload_ps_extra(struct brw_context *brw)
  32 {
  33    struct gl_context *ctx = &brw->ctx;
  34    /* BRW_NEW_FRAGMENT_PROGRAM */
  35    const struct brw_fragment_program *fp =
  36       brw_fragment_program_const(brw->fragment_program);
  37    /* BRW_NEW_FS_PROG_DATA */
  38    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  39    uint32_t dw1 = 0;
  40
  41    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  42
  43    if (prog_data->uses_kill)
  44       dw1 |= GEN8_PSX_KILL_ENABLE;
  45
  46    if (prog_data->num_varying_inputs != 0)
  47       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  48
  49    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  50       switch (fp->program.FragDepthLayout) {
  51          case FRAG_DEPTH_LAYOUT_NONE:
  52          case FRAG_DEPTH_LAYOUT_ANY:
  53             dw1 |= GEN8_PSX_PSCDEPTH_ON;
  54             break;
  55          case FRAG_DEPTH_LAYOUT_GREATER:
  56             dw1 |= GEN8_PSX_PSCDEPTH_ON_GE;
  57             break;
  58          case FRAG_DEPTH_LAYOUT_LESS:
  59             dw1 |= GEN8_PSX_PSCDEPTH_ON_LE;
  60             break;
  61          case FRAG_DEPTH_LAYOUT_UNCHANGED:
  62             break;
  63       }
  64    }
  65
  66    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  67       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  68
  69    /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
  70    bool multisampled_fbo = brw->num_samples > 1;
  71    if (multisampled_fbo &&
  72        _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1)
  73       dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
  74
  75    if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
  76       dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
  77
  78    if (prog_data->uses_omask)
  79       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
  80
  81    BEGIN_BATCH(2);
  82    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
  83    OUT_BATCH(dw1);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state gen8_ps_extra = {
  88    .dirty = {
  89       .mesa  = _NEW_MULTISAMPLE,
  90       .brw   = BRW_NEW_CONTEXT |
  91                BRW_NEW_FRAGMENT_PROGRAM |
  92                BRW_NEW_NUM_SAMPLES,
  93       .cache = BRW_NEW_FS_PROG_DATA,
  94    },
  95    .emit = upload_ps_extra,
  96 };
  97
  98 static void
  99 upload_wm_state(struct brw_context *brw)
 100 {
 101    struct gl_context *ctx = &brw->ctx;
 102    uint32_t dw1 = 0;
 103
 104    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 105    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 106    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 107    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
 108
 109    /* _NEW_LINE */
 110    if (ctx->Line.StippleFlag)
 111       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 112
 113    /* _NEW_POLYGON */
 114    if (ctx->Polygon.StippleFlag)
 115       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 116
 117    /* BRW_NEW_FS_PROG_DATA */
 118    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 119       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 120
 121    BEGIN_BATCH(2);
 122    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 123    OUT_BATCH(dw1);
 124    ADVANCE_BATCH();
 125 }
 126
 127 const struct brw_tracked_state gen8_wm_state = {
 128    .dirty = {
 129       .mesa  = _NEW_LINE |
 130                _NEW_POLYGON,
 131       .brw   = BRW_NEW_CONTEXT,
 132       .cache = BRW_NEW_FS_PROG_DATA,
 133    },
 134    .emit = upload_wm_state,
 135 };
 136
 137 static void
 138 upload_ps_state(struct brw_context *brw)
 139 {
 140    struct gl_context *ctx = &brw->ctx;
 141    uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
 142
 143    /* BRW_NEW_FS_PROG_DATA */
 144    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 145
 146    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 147     * incorrect for subspans where some of the pixels are unlit.  We believe
 148     * the bit just didn't take effect in previous generations.
 149     */
 150    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 151
 152    dw3 |=
 153       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 154
 155    /* BRW_NEW_FS_PROG_DATA */
 156    dw3 |=
 157       ((prog_data->base.binding_table.size_bytes / 4) <<
 158        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 159
 160    /* Use ALT floating point mode for ARB fragment programs, because they
 161     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 162     * rendering, CurrentFragmentProgram is used for this check to
 163     * differentiate between the GLSL and non-GLSL cases.
 164     */
 165    if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 166       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 167
 168    /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
 169     * it implicitly scales for different GT levels (which have some # of PSDs).
 170     */
 171    dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
 172
 173    if (prog_data->base.nr_params > 0)
 174       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 175
 176    /* From the documentation for this packet:
 177     * "If the PS kernel does not need the Position XY Offsets to
 178     *  compute a Position Value, then this field should be programmed
 179     *  to POSOFFSET_NONE."
 180     *
 181     * "SW Recommendation: If the PS kernel needs the Position Offsets
 182     *  to compute a Position XY value, this field should match Position
 183     *  ZW Interpolation Mode to ensure a consistent position.xyzw
 184     *  computation."
 185     *
 186     * We only require XY sample offsets. So, this recommendation doesn't
 187     * look useful at the moment. We might need this in future.
 188     */
 189    if (brw->wm.prog_data->uses_pos_offset)
 190       dw6 |= GEN7_PS_POSOFFSET_SAMPLE;
 191    else
 192       dw6 |= GEN7_PS_POSOFFSET_NONE;
 193
 194    dw6 |= brw->wm.fast_clear_op;
 195
 196    /* _NEW_MULTISAMPLE
 197     * In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 198     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 199     * is successfully compiled. In majority of the cases that bring us
 200     * better performance than 'SIMD8 only' dispatch.
 201     */
 202    int min_invocations_per_fragment =
 203       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
 204    assert(min_invocations_per_fragment >= 1);
 205
 206    if (prog_data->prog_offset_16 || prog_data->no_8) {
 207       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 208       if (!prog_data->no_8 && min_invocations_per_fragment == 1) {
 209          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 210          dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 211                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 212          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 213                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 214          ksp0 = brw->wm.base.prog_offset;
 215          ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
 216       } else {
 217          dw7 |= (prog_data->dispatch_grf_start_reg_16 <<
 218                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 219
 220          ksp0 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
 221       }
 222    } else {
 223       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 224       dw7 |= (prog_data->base.dispatch_grf_start_reg <<
 225               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 226       ksp0 = brw->wm.base.prog_offset;
 227    }
 228
 229    BEGIN_BATCH(12);
 230    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 231    OUT_BATCH(ksp0);
 232    OUT_BATCH(0);
 233    OUT_BATCH(dw3);
 234    if (prog_data->base.total_scratch) {
 235       OUT_RELOC64(brw->wm.base.scratch_bo,
 236                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 237                   ffs(prog_data->base.total_scratch) - 11);
 238    } else {
 239       OUT_BATCH(0);
 240       OUT_BATCH(0);
 241    }
 242    OUT_BATCH(dw6);
 243    OUT_BATCH(dw7);
 244    OUT_BATCH(0); /* kernel 1 pointer */
 245    OUT_BATCH(0);
 246    OUT_BATCH(ksp2);
 247    OUT_BATCH(0);
 248    ADVANCE_BATCH();
 249 }
 250
 251 const struct brw_tracked_state gen8_ps_state = {
 252    .dirty = {
 253       .mesa  = _NEW_MULTISAMPLE,
 254       .brw   = BRW_NEW_BATCH |
 255                BRW_NEW_FRAGMENT_PROGRAM,
 256       .cache = BRW_NEW_FS_PROG_DATA
 257    },
 258    .emit = upload_ps_state,
 259 };