src/mesa/drivers/dri/i965/gen8_ps_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "intel_batchbuffer.h"
  28
  29 static void
  30 upload_ps_extra(struct brw_context *brw)
  31 {
  32    struct gl_context *ctx = &brw->ctx;
  33    /* BRW_NEW_FRAGMENT_PROGRAM */
  34    const struct brw_fragment_program *fp =
  35       brw_fragment_program_const(brw->fragment_program);
  36    uint32_t dw1 = 0;
  37
  38    dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
  39
  40    if (fp->program.UsesKill)
  41       dw1 |= GEN8_PSX_KILL_ENABLE;
  42
  43    /* BRW_NEW_FRAGMENT_PROGRAM */
  44    if (brw->wm.prog_data->num_varying_inputs != 0)
  45       dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
  46
  47    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  48       switch (fp->program.FragDepthLayout) {
  49          case FRAG_DEPTH_LAYOUT_NONE:
  50          case FRAG_DEPTH_LAYOUT_ANY:
  51             dw1 |= GEN8_PSX_PSCDEPTH_ON;
  52             break;
  53          case FRAG_DEPTH_LAYOUT_GREATER:
  54             dw1 |= GEN8_PSX_PSCDEPTH_ON_GE;
  55             break;
  56          case FRAG_DEPTH_LAYOUT_LESS:
  57             dw1 |= GEN8_PSX_PSCDEPTH_ON_LE;
  58             break;
  59          case FRAG_DEPTH_LAYOUT_UNCHANGED:
  60             break;
  61       }
  62    }
  63
  64    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  65       dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
  66
  67    BEGIN_BATCH(2);
  68    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
  69    OUT_BATCH(dw1);
  70    ADVANCE_BATCH();
  71 }
  72
  73 const struct brw_tracked_state gen8_ps_extra = {
  74    .dirty = {
  75       .mesa  = 0,
  76       .brw   = BRW_NEW_CONTEXT | BRW_NEW_FRAGMENT_PROGRAM,
  77       .cache = 0,
  78    },
  79    .emit = upload_ps_extra,
  80 };
  81
  82 static void
  83 upload_wm_state(struct brw_context *brw)
  84 {
  85    struct gl_context *ctx = &brw->ctx;
  86    uint32_t dw1 = 0;
  87
  88    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  89    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  90    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  91    dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
  92
  93    /* _NEW_LINE */
  94    if (ctx->Line.StippleFlag)
  95       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  96
  97    /* _NEW_POLYGON */
  98    if (ctx->Polygon.StippleFlag)
  99       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 100
 101    /* CACHE_NEW_WM_PROG */
 102    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
 103       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 104
 105    BEGIN_BATCH(2);
 106    OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
 107    OUT_BATCH(dw1);
 108    ADVANCE_BATCH();
 109 }
 110
 111 const struct brw_tracked_state gen8_wm_state = {
 112    .dirty = {
 113       .mesa  = _NEW_LINE | _NEW_POLYGON,
 114       .brw   = BRW_NEW_CONTEXT,
 115       .cache = CACHE_NEW_WM_PROG,
 116    },
 117    .emit = upload_wm_state,
 118 };
 119
 120 static void
 121 upload_ps_state(struct brw_context *brw)
 122 {
 123    struct gl_context *ctx = &brw->ctx;
 124    uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
 125
 126    /* BRW_NEW_PS_BINDING_TABLE */
 127    BEGIN_BATCH(2);
 128    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 129    OUT_BATCH(brw->wm.base.bind_bo_offset);
 130    ADVANCE_BATCH();
 131
 132    /* CACHE_NEW_SAMPLER */
 133    BEGIN_BATCH(2);
 134    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 135    OUT_BATCH(brw->wm.base.sampler_offset);
 136    ADVANCE_BATCH();
 137
 138    /* CACHE_NEW_WM_PROG */
 139    gen8_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
 140
 141    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
 142     * incorrect for subspans where some of the pixels are unlit.  We believe
 143     * the bit just didn't take effect in previous generations.
 144     */
 145    dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
 146
 147    /* CACHE_NEW_SAMPLER */
 148    dw3 |=
 149       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 150
 151    /* CACHE_NEW_WM_PROG */
 152    dw3 |=
 153       ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
 154        GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 155
 156    /* Use ALT floating point mode for ARB fragment programs, because they
 157     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 158     * rendering, CurrentFragmentProgram is used for this check to
 159     * differentiate between the GLSL and non-GLSL cases.
 160     */
 161    if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 162       dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 163
 164    dw6 |= (brw->max_wm_threads - 2) << HSW_PS_MAX_THREADS_SHIFT;
 165
 166    /* CACHE_NEW_WM_PROG */
 167    if (brw->wm.prog_data->nr_params > 0)
 168       dw6 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 169
 170    dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
 171    if (brw->wm.prog_data->prog_offset_16)
 172       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
 173
 174    dw7 |=
 175       brw->wm.prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0 |
 176       brw->wm.prog_data->first_curbe_grf_16<< GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 177
 178    BEGIN_BATCH(12);
 179    OUT_BATCH(_3DSTATE_PS << 16 | (12 - 2));
 180    OUT_BATCH(brw->wm.base.prog_offset);
 181    OUT_BATCH(0);
 182    OUT_BATCH(dw3);
 183    if (brw->wm.prog_data->total_scratch) {
 184       OUT_RELOC64(brw->wm.base.scratch_bo,
 185                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 186                   ffs(brw->wm.prog_data->total_scratch) - 11);
 187    } else {
 188       OUT_BATCH(0);
 189       OUT_BATCH(0);
 190    }
 191    OUT_BATCH(dw6);
 192    OUT_BATCH(dw7);
 193    OUT_BATCH(0); /* kernel 1 pointer */
 194    OUT_BATCH(0);
 195    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 196    OUT_BATCH(0);
 197    ADVANCE_BATCH();
 198 }
 199
 200 const struct brw_tracked_state gen8_ps_state = {
 201    .dirty = {
 202       .mesa  = _NEW_PROGRAM_CONSTANTS,
 203       .brw   = BRW_NEW_FRAGMENT_PROGRAM |
 204                BRW_NEW_PS_BINDING_TABLE |
 205                BRW_NEW_BATCH |
 206                BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 207       .cache = CACHE_NEW_SAMPLER | CACHE_NEW_WM_PROG
 208    },
 209    .emit = upload_ps_state,
 210 };