2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/blend.h"
25 #include "main/mtypes.h"
26 #include "main/samplerobj.h"
27 #include "main/texformat.h"
28 #include "program/prog_parameter.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_batchbuffer.h"
32 #include "intel_tex.h"
33 #include "intel_fbo.h"
34 #include "intel_buffer_objects.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_defines.h"
42 surface_tiling_mode(uint32_t tiling
)
46 return GEN8_SURFACE_TILING_X
;
48 return GEN8_SURFACE_TILING_Y
;
50 return GEN8_SURFACE_TILING_NONE
;
55 vertical_alignment(struct intel_mipmap_tree
*mt
)
57 switch (mt
->align_h
) {
59 return GEN8_SURFACE_VALIGN_4
;
61 return GEN8_SURFACE_VALIGN_8
;
63 return GEN8_SURFACE_VALIGN_16
;
65 unreachable("Unsupported vertical surface alignment.");
70 horizontal_alignment(struct intel_mipmap_tree
*mt
)
72 switch (mt
->align_w
) {
74 return GEN8_SURFACE_HALIGN_4
;
76 return GEN8_SURFACE_HALIGN_8
;
78 return GEN8_SURFACE_HALIGN_16
;
80 unreachable("Unsupported horizontal surface alignment.");
85 gen8_emit_buffer_surface_state(struct brw_context
*brw
,
88 unsigned buffer_offset
,
89 unsigned surface_format
,
95 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
96 13 * 4, 64, out_offset
);
97 memset(surf
, 0, 13 * 4);
99 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
100 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
101 BRW_SURFACE_RC_READ_WRITE
;
102 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
);
104 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
105 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
106 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
) |
108 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
109 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
110 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
111 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
113 *((uint64_t *) &surf
[8]) = (bo
? bo
->offset64
: 0) + buffer_offset
;
115 /* Emit relocation to surface contents. */
117 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 8 * 4,
118 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
119 rw
? I915_GEM_DOMAIN_SAMPLER
: 0);
124 gen8_update_texture_surface(struct gl_context
*ctx
,
126 uint32_t *surf_offset
,
129 struct brw_context
*brw
= brw_context(ctx
);
130 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
131 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
132 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
133 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
134 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
135 struct intel_mipmap_tree
*aux_mt
= NULL
;
136 uint32_t aux_mode
= 0;
137 mesa_format format
= intelObj
->_Format
;
139 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
140 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
144 if (tObj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
146 format
= MESA_FORMAT_S_UINT8
;
149 unsigned tiling_mode
, pitch
;
150 if (format
== MESA_FORMAT_S_UINT8
) {
151 tiling_mode
= GEN8_SURFACE_TILING_W
;
152 pitch
= 2 * mt
->pitch
;
154 tiling_mode
= surface_tiling_mode(mt
->tiling
);
160 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
163 /* If this is a view with restricted NumLayers, then our effective depth
164 * is not just the miptree depth.
166 uint32_t effective_depth
=
167 (tObj
->Immutable
&& tObj
->Target
!= GL_TEXTURE_3D
) ? tObj
->NumLayers
168 : mt
->logical_depth0
;
170 uint32_t tex_format
= translate_tex_format(brw
, format
, sampler
->sRGBDecode
);
172 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
173 13 * 4, 64, surf_offset
);
175 surf
[0] = translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
176 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
|
177 vertical_alignment(mt
) |
178 horizontal_alignment(mt
) |
181 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
||
182 tObj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
183 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
186 if (mt
->logical_depth0
> 1 && tObj
->Target
!= GL_TEXTURE_3D
)
187 surf
[0] |= GEN8_SURFACE_IS_ARRAY
;
189 surf
[1] = SET_FIELD(BDW_MOCS_WB
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
191 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
192 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
194 surf
[3] = SET_FIELD(effective_depth
- 1, BRW_SURFACE_DEPTH
) | (pitch
- 1);
196 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
) |
197 SET_FIELD(tObj
->MinLayer
, GEN7_SURFACE_MIN_ARRAY_ELEMENT
) |
198 SET_FIELD(effective_depth
- 1,
199 GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT
);
201 surf
[5] = SET_FIELD(tObj
->MinLevel
+ tObj
->BaseLevel
- mt
->first_level
,
202 GEN7_SURFACE_MIN_LOD
) |
203 (intelObj
->_MaxLevel
- tObj
->BaseLevel
); /* mip count */
206 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
207 SET_FIELD((aux_mt
->pitch
/ 128) - 1, GEN8_SURFACE_AUX_PITCH
) |
213 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
214 * texturing functions that return a float, as our code generation always
215 * selects the .x channel (which would always be 0).
217 const bool alpha_depth
= tObj
->DepthMode
== GL_ALPHA
&&
218 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
219 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
221 surf
[7] = mt
->fast_clear_color_value
;
224 unlikely(alpha_depth
) ? SWIZZLE_XYZW
: brw_get_texture_swizzle(ctx
, tObj
);
226 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 0), false), GEN7_SURFACE_SCS_R
) |
227 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 1), false), GEN7_SURFACE_SCS_G
) |
228 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 2), false), GEN7_SURFACE_SCS_B
) |
229 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 3), false), GEN7_SURFACE_SCS_A
);
231 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
234 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
235 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *surf_offset
+ 10 * 4,
237 I915_GEM_DOMAIN_SAMPLER
, 0);
244 /* Emit relocation to surface contents */
245 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
246 *surf_offset
+ 8 * 4,
249 I915_GEM_DOMAIN_SAMPLER
, 0);
253 gen8_create_raw_surface(struct brw_context
*brw
, drm_intel_bo
*bo
,
254 uint32_t offset
, uint32_t size
,
255 uint32_t *out_offset
, bool rw
)
257 gen8_emit_buffer_surface_state(brw
,
261 BRW_SURFACEFORMAT_RAW
,
269 * Creates a null renderbuffer surface.
271 * This is used when the shader doesn't write to any color output. An FB
272 * write to target 0 will still be emitted, because that's how the thread is
273 * terminated (and computed depth is returned), so we need to have the
274 * hardware discard the target 0 color output..
277 gen8_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned unit
)
279 struct gl_context
*ctx
= &brw
->ctx
;
282 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
283 uint32_t surf_index
=
284 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
286 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 13 * 4, 64,
287 &brw
->wm
.base
.surf_offset
[surf_index
]);
288 memset(surf
, 0, 13 * 4);
290 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
291 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
292 GEN8_SURFACE_TILING_Y
;
293 surf
[2] = SET_FIELD(fb
->Width
- 1, GEN7_SURFACE_WIDTH
) |
294 SET_FIELD(fb
->Height
- 1, GEN7_SURFACE_HEIGHT
);
298 * Sets up a surface state structure to point at the given region.
299 * While it is only used for the front/back buffer currently, it should be
300 * usable for further buffers when doing ARB_draw_buffer support.
303 gen8_update_renderbuffer_surface(struct brw_context
*brw
,
304 struct gl_renderbuffer
*rb
,
308 struct gl_context
*ctx
= &brw
->ctx
;
309 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
310 struct intel_mipmap_tree
*mt
= irb
->mt
;
311 struct intel_mipmap_tree
*aux_mt
= NULL
;
312 uint32_t aux_mode
= 0;
313 unsigned width
= mt
->logical_width0
;
314 unsigned height
= mt
->logical_height0
;
315 unsigned pitch
= mt
->pitch
;
316 uint32_t tiling
= mt
->tiling
;
319 bool is_array
= false;
320 int depth
= MAX2(irb
->layer_count
, 1);
321 const int min_array_element
= (mt
->format
== MESA_FORMAT_S_UINT8
) ?
322 irb
->mt_layer
: (irb
->mt_layer
/ MAX2(mt
->num_samples
, 1));
324 rb
->TexImage
? rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
326 uint32_t surf_index
=
327 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
329 intel_miptree_used_for_rendering(mt
);
332 case GL_TEXTURE_CUBE_MAP_ARRAY
:
333 case GL_TEXTURE_CUBE_MAP
:
334 surf_type
= BRW_SURFACE_2D
;
339 depth
= MAX2(irb
->mt
->logical_depth0
, 1);
342 surf_type
= translate_tex_target(gl_target
);
343 is_array
= _mesa_tex_target_is_array(gl_target
);
348 /* Render targets can't use IMS layout. Stencil in turn gets configured as
349 * single sampled and indexed manually by the program.
351 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
352 brw_configure_w_tiled(mt
, true, &width
, &height
, &pitch
,
355 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
356 assert(brw_render_target_supported(brw
, rb
));
357 mesa_format rb_format
= _mesa_get_render_format(ctx
,
358 intel_rb_format(irb
));
359 format
= brw
->render_target_format
[rb_format
];
360 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
]))
361 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
362 __FUNCTION__
, _mesa_get_format_name(rb_format
));
367 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
370 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 13 * 4, 64,
371 &brw
->wm
.base
.surf_offset
[surf_index
]);
373 surf
[0] = (surf_type
<< BRW_SURFACE_TYPE_SHIFT
) |
374 (is_array
? GEN7_SURFACE_IS_ARRAY
: 0) |
375 (format
<< BRW_SURFACE_FORMAT_SHIFT
) |
376 vertical_alignment(mt
) |
377 horizontal_alignment(mt
) |
378 surface_tiling_mode(tiling
);
380 surf
[1] = SET_FIELD(BDW_MOCS_WT
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
382 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
383 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
385 surf
[3] = (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
386 (pitch
- 1); /* Surface Pitch */
388 surf
[4] = min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
389 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
391 if (mt
->format
!= MESA_FORMAT_S_UINT8
)
392 surf
[4] |= gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
394 surf
[5] = irb
->mt_level
- irb
->mt
->first_level
;
397 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
398 SET_FIELD((aux_mt
->pitch
/ 128) - 1, GEN8_SURFACE_AUX_PITCH
) |
404 surf
[7] = mt
->fast_clear_color_value
|
405 SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
406 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
407 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
408 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
410 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
; /* reloc */
413 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
414 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
415 brw
->wm
.base
.surf_offset
[surf_index
] + 10 * 4,
417 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
424 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
425 brw
->wm
.base
.surf_offset
[surf_index
] + 8 * 4,
428 I915_GEM_DOMAIN_RENDER
,
429 I915_GEM_DOMAIN_RENDER
);
433 gen8_init_vtable_surface_functions(struct brw_context
*brw
)
435 brw
->vtbl
.update_texture_surface
= gen8_update_texture_surface
;
436 brw
->vtbl
.update_renderbuffer_surface
= gen8_update_renderbuffer_surface
;
437 brw
->vtbl
.update_null_renderbuffer_surface
=
438 gen8_update_null_renderbuffer_surface
;
439 brw
->vtbl
.create_raw_surface
= gen8_create_raw_surface
;
440 brw
->vtbl
.emit_buffer_surface_state
= gen8_emit_buffer_surface_state
;