src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "program/prog_parameter.h"
  29
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "intel_tex.h"
  33 #include "intel_fbo.h"
  34 #include "intel_buffer_objects.h"
  35
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40
  41 static uint32_t
  42 surface_tiling_mode(uint32_t tiling)
  43 {
  44    switch (tiling) {
  45    case I915_TILING_X:
  46       return GEN8_SURFACE_TILING_X;
  47    case I915_TILING_Y:
  48       return GEN8_SURFACE_TILING_Y;
  49    default:
  50       return GEN8_SURFACE_TILING_NONE;
  51    }
  52 }
  53
  54 static unsigned
  55 vertical_alignment(struct intel_mipmap_tree *mt)
  56 {
  57    switch (mt->align_h) {
  58    case 4:
  59       return GEN8_SURFACE_VALIGN_4;
  60    case 8:
  61       return GEN8_SURFACE_VALIGN_8;
  62    case 16:
  63       return GEN8_SURFACE_VALIGN_16;
  64    default:
  65       assert(!"Unsupported vertical surface alignment.");
  66       return GEN8_SURFACE_VALIGN_4;
  67    }
  68 }
  69
  70 static unsigned
  71 horizontal_alignment(struct intel_mipmap_tree *mt)
  72 {
  73    switch (mt->align_w) {
  74    case 4:
  75       return GEN8_SURFACE_HALIGN_4;
  76    case 8:
  77       return GEN8_SURFACE_HALIGN_8;
  78    case 16:
  79       return GEN8_SURFACE_HALIGN_16;
  80    default:
  81       assert(!"Unsupported horizontal surface alignment.");
  82       return GEN8_SURFACE_HALIGN_4;
  83    }
  84 }
  85
  86 static void
  87 gen8_emit_buffer_surface_state(struct brw_context *brw,
  88                                uint32_t *out_offset,
  89                                drm_intel_bo *bo,
  90                                unsigned buffer_offset,
  91                                unsigned surface_format,
  92                                unsigned buffer_size,
  93                                unsigned pitch,
  94                                unsigned mocs,
  95                                bool rw)
  96 {
  97    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  98                                     13 * 4, 64, out_offset);
  99    memset(surf, 0, 13 * 4);
 100
 101    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 102              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 103              BRW_SURFACE_RC_READ_WRITE;
 104
 105    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 106              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 107    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 108              (pitch - 1);
 109    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 110              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 111              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 112              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 113    /* reloc */
 114    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 115
 116    /* Emit relocation to surface contents. */
 117    if (bo) {
 118       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 119                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 120                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 121    }
 122 }
 123
 124 static void
 125 gen8_update_texture_surface(struct gl_context *ctx,
 126                             unsigned unit,
 127                             uint32_t *surf_offset,
 128                             bool for_gather)
 129 {
 130    struct brw_context *brw = brw_context(ctx);
 131    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 132    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 133    struct intel_mipmap_tree *mt = intelObj->mt;
 134    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 135    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 136
 137    if (tObj->Target == GL_TEXTURE_BUFFER) {
 138       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 139       return;
 140    }
 141
 142    uint32_t tex_format = translate_tex_format(brw,
 143                                               mt->format,
 144                                               sampler->sRGBDecode);
 145
 146    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 147                                     13 * 4, 64, surf_offset);
 148
 149    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 150              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 151              vertical_alignment(mt) |
 152              horizontal_alignment(mt) |
 153              surface_tiling_mode(mt->region->tiling);
 154
 155    if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
 156        tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
 157       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 158    }
 159
 160    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 161       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 162
 163    surf[1] = mt->qpitch >> 2;
 164
 165    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 166              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 167
 168    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
 169              (mt->region->pitch - 1);
 170
 171    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 172
 173    surf[5] = SET_FIELD(tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 174              (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
 175
 176    surf[6] = 0;
 177
 178    /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 179     * texturing functions that return a float, as our code generation always
 180     * selects the .x channel (which would always be 0).
 181     */
 182    const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 183       (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 184        firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 185
 186    const int swizzle =
 187       unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 188    surf[7] =
 189       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), false), GEN7_SURFACE_SCS_R) |
 190       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), false), GEN7_SURFACE_SCS_G) |
 191       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
 192       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
 193
 194    *((uint64_t *) &surf[8]) = mt->region->bo->offset64 + mt->offset; /* reloc */
 195
 196    surf[10] = 0;
 197    surf[11] = 0;
 198    surf[12] = 0;
 199
 200    /* Emit relocation to surface contents */
 201    drm_intel_bo_emit_reloc(brw->batch.bo,
 202                            *surf_offset + 8 * 4,
 203                            mt->region->bo,
 204                            mt->offset,
 205                            I915_GEM_DOMAIN_SAMPLER, 0);
 206 }
 207
 208 /**
 209  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 210  * read from this buffer with Data Port Read instructions/messages.
 211  */
 212 static void
 213 gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 214 {
 215    struct gl_context *ctx = &brw->ctx;
 216
 217    /* _NEW_BUFFERS */
 218    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 219    uint32_t surf_index =
 220       brw->wm.prog_data->binding_table.render_target_start + unit;
 221
 222    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
 223                                     &brw->wm.base.surf_offset[surf_index]);
 224    memset(surf, 0, 13 * 4);
 225
 226    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 227              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 228              GEN8_SURFACE_TILING_Y;
 229    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 230              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 231 }
 232
 233 /**
 234  * Sets up a surface state structure to point at the given region.
 235  * While it is only used for the front/back buffer currently, it should be
 236  * usable for further buffers when doing ARB_draw_buffer support.
 237  */
 238 static void
 239 gen8_update_renderbuffer_surface(struct brw_context *brw,
 240                                  struct gl_renderbuffer *rb,
 241                                  bool layered,
 242                                  unsigned unit)
 243 {
 244    struct gl_context *ctx = &brw->ctx;
 245    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 246    struct intel_mipmap_tree *mt = irb->mt;
 247    struct intel_region *region = mt->region;
 248    uint32_t format = 0;
 249    uint32_t surf_type;
 250    bool is_array = false;
 251    int depth = MAX2(rb->Depth, 1);
 252    int min_array_element;
 253
 254    GLenum gl_target =
 255       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 256
 257    uint32_t surf_index =
 258       brw->wm.prog_data->binding_table.render_target_start + unit;
 259
 260    intel_miptree_used_for_rendering(mt);
 261
 262    /* Render targets can't use IMS layout. */
 263    assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 264
 265    switch (gl_target) {
 266    case GL_TEXTURE_CUBE_MAP_ARRAY:
 267    case GL_TEXTURE_CUBE_MAP:
 268       surf_type = BRW_SURFACE_2D;
 269       is_array = true;
 270       depth *= 6;
 271       break;
 272    default:
 273       surf_type = translate_tex_target(gl_target);
 274       is_array = _mesa_tex_target_is_array(gl_target);
 275       break;
 276    }
 277
 278    if (layered) {
 279       min_array_element = 0;
 280    } else if (mt->num_samples > 1) {
 281       min_array_element = irb->mt_layer / mt->num_samples;
 282    } else {
 283       min_array_element = irb->mt_layer;
 284    }
 285
 286    /* _NEW_BUFFERS */
 287    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 288    assert(brw_render_target_supported(brw, rb));
 289    format = brw->render_target_format[rb_format];
 290    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 291       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 292                     __FUNCTION__, _mesa_get_format_name(rb_format));
 293    }
 294
 295    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
 296                                     &brw->wm.base.surf_offset[surf_index]);
 297
 298    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 299              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 300              (format << BRW_SURFACE_FORMAT_SHIFT) |
 301              vertical_alignment(mt) |
 302              horizontal_alignment(mt) |
 303              surface_tiling_mode(region->tiling);
 304
 305    surf[1] = mt->qpitch >> 2;
 306
 307    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 308              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 309
 310    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 311              (region->pitch - 1); /* Surface Pitch */
 312
 313    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 314              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 315              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 316
 317    surf[5] = irb->mt_level - irb->mt->first_level;
 318
 319    surf[6] = 0; /* Nothing of relevance. */
 320
 321    surf[7] = mt->fast_clear_color_value |
 322              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 323              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 324              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 325              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 326
 327    *((uint64_t *) &surf[8]) = region->bo->offset64; /* reloc */
 328
 329    /* Nothing of relevance. */
 330    surf[10] = 0;
 331    surf[11] = 0;
 332    surf[12] = 0;
 333
 334    drm_intel_bo_emit_reloc(brw->batch.bo,
 335                            brw->wm.base.surf_offset[surf_index] + 8 * 4,
 336                            region->bo,
 337                            0,
 338                            I915_GEM_DOMAIN_RENDER,
 339                            I915_GEM_DOMAIN_RENDER);
 340 }
 341
 342 void
 343 gen8_init_vtable_surface_functions(struct brw_context *brw)
 344 {
 345    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 346    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 347    brw->vtbl.update_null_renderbuffer_surface =
 348       gen8_update_null_renderbuffer_surface;
 349    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 350 }