src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "main/teximage.h"
  29 #include "program/prog_parameter.h"
  30
  31 #include "intel_mipmap_tree.h"
  32 #include "intel_batchbuffer.h"
  33 #include "intel_tex.h"
  34 #include "intel_fbo.h"
  35 #include "intel_buffer_objects.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40 #include "brw_wm.h"
  41
  42 /**
  43  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  44  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
  45  *
  46  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
  47  *         0          1          2          3             4            5
  48  *         4          5          6          7             0            1
  49  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
  50  *
  51  * which is simply adding 4 then modding by 8 (or anding with 7).
  52  */
  53 static unsigned
  54 swizzle_to_scs(unsigned swizzle)
  55 {
  56    return (swizzle + 4) & 7;
  57 }
  58
  59 static uint32_t
  60 surface_tiling_resource_mode(uint32_t tr_mode)
  61 {
  62    switch (tr_mode) {
  63    case INTEL_MIPTREE_TRMODE_YF:
  64       return GEN9_SURFACE_TRMODE_TILEYF;
  65    case INTEL_MIPTREE_TRMODE_YS:
  66       return GEN9_SURFACE_TRMODE_TILEYS;
  67    default:
  68       return GEN9_SURFACE_TRMODE_NONE;
  69    }
  70 }
  71
  72 static uint32_t
  73 surface_tiling_mode(uint32_t tiling)
  74 {
  75    switch (tiling) {
  76    case I915_TILING_X:
  77       return GEN8_SURFACE_TILING_X;
  78    case I915_TILING_Y:
  79       return GEN8_SURFACE_TILING_Y;
  80    default:
  81       return GEN8_SURFACE_TILING_NONE;
  82    }
  83 }
  84
  85 static unsigned
  86 vertical_alignment(const struct brw_context *brw,
  87                    const struct intel_mipmap_tree *mt,
  88                    uint32_t surf_type)
  89 {
  90    /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
  91     * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
  92     */
  93    if (brw->gen > 8 &&
  94        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
  95         surf_type == BRW_SURFACE_1D))
  96       return GEN8_SURFACE_VALIGN_4;
  97
  98    switch (mt->align_h) {
  99    case 4:
 100       return GEN8_SURFACE_VALIGN_4;
 101    case 8:
 102       return GEN8_SURFACE_VALIGN_8;
 103    case 16:
 104       return GEN8_SURFACE_VALIGN_16;
 105    default:
 106       unreachable("Unsupported vertical surface alignment.");
 107    }
 108 }
 109
 110 static unsigned
 111 horizontal_alignment(const struct brw_context *brw,
 112                      const struct intel_mipmap_tree *mt,
 113                      uint32_t surf_type)
 114 {
 115    /* On Gen9+ horizontal alignment is ignored when tr_mode is not
 116     * TRMODE_NONE. Set to an arbitrary non-reserved value.
 117     */
 118    if (brw->gen > 8 &&
 119        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 120         gen9_use_linear_1d_layout(brw, mt)))
 121       return GEN8_SURFACE_HALIGN_4;
 122
 123    switch (mt->align_w) {
 124    case 4:
 125       return GEN8_SURFACE_HALIGN_4;
 126    case 8:
 127       return GEN8_SURFACE_HALIGN_8;
 128    case 16:
 129       return GEN8_SURFACE_HALIGN_16;
 130    default:
 131       unreachable("Unsupported horizontal surface alignment.");
 132    }
 133 }
 134
 135 static uint32_t *
 136 allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
 137 {
 138    int dwords = brw->gen >= 9 ? 16 : 13;
 139    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 140                                       dwords * 4, 64, index, out_offset);
 141    memset(surf, 0, dwords * 4);
 142    return surf;
 143 }
 144
 145 static void
 146 gen8_emit_buffer_surface_state(struct brw_context *brw,
 147                                uint32_t *out_offset,
 148                                drm_intel_bo *bo,
 149                                unsigned buffer_offset,
 150                                unsigned surface_format,
 151                                unsigned buffer_size,
 152                                unsigned pitch,
 153                                bool rw)
 154 {
 155    const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 156    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 157
 158    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 159              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 160              BRW_SURFACE_RC_READ_WRITE;
 161    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
 162
 163    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 164              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 165    if (surface_format == BRW_SURFACEFORMAT_RAW)
 166       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
 167    else
 168       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 169    surf[3] |= (pitch - 1);
 170    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 171              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 172              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 173              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 174    /* reloc */
 175    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 176
 177    /* Emit relocation to surface contents. */
 178    if (bo) {
 179       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 180                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 181                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 182    }
 183 }
 184
 185 static void
 186 gen8_emit_texture_surface_state(struct brw_context *brw,
 187                                 struct intel_mipmap_tree *mt,
 188                                 GLenum target,
 189                                 unsigned min_layer, unsigned max_layer,
 190                                 unsigned min_level, unsigned max_level,
 191                                 unsigned format,
 192                                 unsigned swizzle,
 193                                 uint32_t *surf_offset,
 194                                 bool rw, bool for_gather)
 195 {
 196    const unsigned depth = max_layer - min_layer;
 197    struct intel_mipmap_tree *aux_mt = NULL;
 198    uint32_t aux_mode = 0;
 199    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 200    int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
 201    unsigned tiling_mode, pitch;
 202    const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 203
 204    if (mt->format == MESA_FORMAT_S_UINT8) {
 205       tiling_mode = GEN8_SURFACE_TILING_W;
 206       pitch = 2 * mt->pitch;
 207    } else {
 208       tiling_mode = surface_tiling_mode(mt->tiling);
 209       pitch = mt->pitch;
 210    }
 211
 212    if (mt->mcs_mt) {
 213       aux_mt = mt->mcs_mt;
 214       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 215
 216       /*
 217        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 218        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 219        *
 220        * From the hardware spec for GEN9:
 221        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 222        *  16 must be used."
 223        */
 224       assert(brw->gen < 9 || mt->align_w == 16);
 225       assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16);
 226    }
 227
 228    const uint32_t surf_type = translate_tex_target(target);
 229    uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
 230
 231    surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
 232              format << BRW_SURFACE_FORMAT_SHIFT |
 233              vertical_alignment(brw, mt, surf_type) |
 234              horizontal_alignment(brw, mt, surf_type) |
 235              tiling_mode;
 236
 237    if (surf_type == BRW_SURFACE_CUBE) {
 238       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 239    }
 240
 241    if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
 242       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 243
 244    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 245
 246    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 247              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 248
 249    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 250
 251    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 252              SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 253              SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 254
 255    surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 256              (max_level - min_level - 1); /* mip count */
 257
 258    if (brw->gen >= 9) {
 259       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 260       /* Disable Mip Tail by setting a large value. */
 261       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 262    }
 263
 264    if (aux_mt) {
 265       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 266                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
 267                 aux_mode;
 268    } else {
 269       surf[6] = 0;
 270    }
 271
 272    surf[7] = mt->fast_clear_color_value |
 273       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 274       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 275       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 276       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 277
 278    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 279
 280    if (aux_mt) {
 281       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 282       drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
 283                               aux_mt->bo, 0,
 284                               I915_GEM_DOMAIN_SAMPLER,
 285                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 286    } else {
 287       surf[10] = 0;
 288       surf[11] = 0;
 289    }
 290    surf[12] = 0;
 291
 292    /* Emit relocation to surface contents */
 293    drm_intel_bo_emit_reloc(brw->batch.bo,
 294                            *surf_offset + 8 * 4,
 295                            mt->bo,
 296                            mt->offset,
 297                            I915_GEM_DOMAIN_SAMPLER,
 298                            (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 299 }
 300
 301 static void
 302 gen8_update_texture_surface(struct gl_context *ctx,
 303                             unsigned unit,
 304                             uint32_t *surf_offset,
 305                             bool for_gather)
 306 {
 307    struct brw_context *brw = brw_context(ctx);
 308    struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
 309
 310    if (obj->Target == GL_TEXTURE_BUFFER) {
 311       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 312
 313    } else {
 314       struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
 315       struct intel_texture_object *intel_obj = intel_texture_object(obj);
 316       struct intel_mipmap_tree *mt = intel_obj->mt;
 317       struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 318       /* If this is a view with restricted NumLayers, then our effective depth
 319        * is not just the miptree depth.
 320        */
 321       const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
 322                               obj->NumLayers : mt->logical_depth0);
 323
 324       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 325        * texturing functions that return a float, as our code generation always
 326        * selects the .x channel (which would always be 0).
 327        */
 328       const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
 329          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 330           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 331       const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
 332                                 brw_get_texture_swizzle(&brw->ctx, obj));
 333
 334       unsigned format = translate_tex_format(brw, intel_obj->_Format,
 335                                              sampler->sRGBDecode);
 336       if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
 337          mt = mt->stencil_mt;
 338          format = BRW_SURFACEFORMAT_R8_UINT;
 339       }
 340
 341       gen8_emit_texture_surface_state(brw, mt, obj->Target,
 342                                       obj->MinLayer, obj->MinLayer + depth,
 343                                       obj->MinLevel + obj->BaseLevel,
 344                                       obj->MinLevel + intel_obj->_MaxLevel + 1,
 345                                       format, swizzle, surf_offset,
 346                                       false, for_gather);
 347    }
 348 }
 349
 350 /**
 351  * Creates a null surface.
 352  *
 353  * This is used when the shader doesn't write to any color output.  An FB
 354  * write to target 0 will still be emitted, because that's how the thread is
 355  * terminated (and computed depth is returned), so we need to have the
 356  * hardware discard the target 0 color output..
 357  */
 358 static void
 359 gen8_emit_null_surface_state(struct brw_context *brw,
 360                              unsigned width,
 361                              unsigned height,
 362                              unsigned samples,
 363                              uint32_t *out_offset)
 364 {
 365    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 366
 367    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 368              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 369              GEN8_SURFACE_TILING_Y;
 370    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 371              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 372 }
 373
 374 /**
 375  * Sets up a surface state structure to point at the given region.
 376  * While it is only used for the front/back buffer currently, it should be
 377  * usable for further buffers when doing ARB_draw_buffer support.
 378  */
 379 static uint32_t
 380 gen8_update_renderbuffer_surface(struct brw_context *brw,
 381                                  struct gl_renderbuffer *rb,
 382                                  bool layered, unsigned unit /* unused */,
 383                                  uint32_t surf_index)
 384 {
 385    struct gl_context *ctx = &brw->ctx;
 386    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 387    struct intel_mipmap_tree *mt = irb->mt;
 388    struct intel_mipmap_tree *aux_mt = NULL;
 389    uint32_t aux_mode = 0;
 390    unsigned width = mt->logical_width0;
 391    unsigned height = mt->logical_height0;
 392    unsigned pitch = mt->pitch;
 393    uint32_t tiling = mt->tiling;
 394    unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 395    uint32_t format = 0;
 396    uint32_t surf_type;
 397    uint32_t offset;
 398    bool is_array = false;
 399    int depth = MAX2(irb->layer_count, 1);
 400    const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
 401       irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
 402    GLenum gl_target =
 403       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 404    const uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE;
 405
 406    intel_miptree_used_for_rendering(mt);
 407
 408    switch (gl_target) {
 409    case GL_TEXTURE_CUBE_MAP_ARRAY:
 410    case GL_TEXTURE_CUBE_MAP:
 411       surf_type = BRW_SURFACE_2D;
 412       is_array = true;
 413       depth *= 6;
 414       break;
 415    case GL_TEXTURE_3D:
 416       depth = MAX2(irb->mt->logical_depth0, 1);
 417       /* fallthrough */
 418    default:
 419       surf_type = translate_tex_target(gl_target);
 420       is_array = _mesa_tex_target_is_array(gl_target);
 421       break;
 422    }
 423
 424    /* _NEW_BUFFERS */
 425    /* Render targets can't use IMS layout. Stencil in turn gets configured as
 426     * single sampled and indexed manually by the program.
 427     */
 428    if (mt->format == MESA_FORMAT_S_UINT8) {
 429       brw_configure_w_tiled(mt, true, &width, &height, &pitch,
 430                             &tiling, &format);
 431    } else {
 432       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 433       assert(brw_render_target_supported(brw, rb));
 434       mesa_format rb_format = _mesa_get_render_format(ctx,
 435                                                       intel_rb_format(irb));
 436       format = brw->render_target_format[rb_format];
 437       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
 438          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 439                        __func__, _mesa_get_format_name(rb_format));
 440    }
 441
 442    if (mt->mcs_mt) {
 443       aux_mt = mt->mcs_mt;
 444       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 445
 446       /*
 447        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 448        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 449        *
 450        * From the hardware spec for GEN9:
 451        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 452        *  16 must be used."
 453        */
 454       assert(brw->gen < 9 || mt->align_w == 16);
 455       assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16);
 456    }
 457
 458    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
 459
 460    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 461              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 462              (format << BRW_SURFACE_FORMAT_SHIFT) |
 463              vertical_alignment(brw, mt, surf_type) |
 464              horizontal_alignment(brw, mt, surf_type) |
 465              surface_tiling_mode(tiling);
 466
 467    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 468
 469    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 470              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 471
 472    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 473              (pitch - 1); /* Surface Pitch */
 474
 475    surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 476              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 477
 478    if (mt->format != MESA_FORMAT_S_UINT8)
 479       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 480
 481    surf[5] = irb->mt_level - irb->mt->first_level;
 482
 483    if (brw->gen >= 9) {
 484       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 485       /* Disable Mip Tail by setting a large value. */
 486       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 487    }
 488
 489    if (aux_mt) {
 490       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 491                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
 492                 aux_mode;
 493    } else {
 494       surf[6] = 0;
 495    }
 496
 497    surf[7] = mt->fast_clear_color_value |
 498              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 499              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 500              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 501              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 502
 503    assert(mt->offset % mt->cpp == 0);
 504    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 505
 506    if (aux_mt) {
 507       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 508       drm_intel_bo_emit_reloc(brw->batch.bo,
 509                               offset + 10 * 4,
 510                               aux_mt->bo, 0,
 511                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 512    } else {
 513       surf[10] = 0;
 514       surf[11] = 0;
 515    }
 516    surf[12] = 0;
 517
 518    drm_intel_bo_emit_reloc(brw->batch.bo,
 519                            offset + 8 * 4,
 520                            mt->bo,
 521                            mt->offset,
 522                            I915_GEM_DOMAIN_RENDER,
 523                            I915_GEM_DOMAIN_RENDER);
 524
 525    return offset;
 526 }
 527
 528 void
 529 gen8_init_vtable_surface_functions(struct brw_context *brw)
 530 {
 531    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 532    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 533    brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
 534    brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
 535    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 536 }