src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "main/teximage.h"
  29 #include "program/prog_parameter.h"
  30 #include "program/prog_instruction.h"
  31
  32 #include "intel_mipmap_tree.h"
  33 #include "intel_batchbuffer.h"
  34 #include "intel_tex.h"
  35 #include "intel_fbo.h"
  36 #include "intel_buffer_objects.h"
  37 #include "intel_image.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42 #include "brw_wm.h"
  43 #include "isl/isl.h"
  44
  45 static uint32_t *
  46 gen8_allocate_surface_state(struct brw_context *brw,
  47                             uint32_t *out_offset, int index)
  48 {
  49    int dwords = brw->gen >= 9 ? 16 : 13;
  50    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  51                                       dwords * 4, 64, index, out_offset);
  52    memset(surf, 0, dwords * 4);
  53    return surf;
  54 }
  55
  56 static void
  57 gen8_emit_buffer_surface_state(struct brw_context *brw,
  58                                uint32_t *out_offset,
  59                                drm_intel_bo *bo,
  60                                unsigned buffer_offset,
  61                                unsigned surface_format,
  62                                unsigned buffer_size,
  63                                unsigned pitch,
  64                                bool rw)
  65 {
  66    unsigned elements = buffer_size / pitch;
  67    const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  68    uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
  69
  70    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
  71              surface_format << BRW_SURFACE_FORMAT_SHIFT |
  72              BRW_SURFACE_RC_READ_WRITE;
  73    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
  74
  75    surf[2] = SET_FIELD((elements - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
  76              SET_FIELD(((elements - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
  77    if (surface_format == BRW_SURFACEFORMAT_RAW)
  78       surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
  79    else
  80       surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
  81    surf[3] |= (pitch - 1);
  82    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
  83              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
  84              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
  85              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
  86    /* reloc */
  87    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
  88
  89    /* Emit relocation to surface contents. */
  90    if (bo) {
  91       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
  92                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
  93                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
  94    }
  95 }
  96
  97 /**
  98  * Creates a null surface.
  99  *
 100  * This is used when the shader doesn't write to any color output.  An FB
 101  * write to target 0 will still be emitted, because that's how the thread is
 102  * terminated (and computed depth is returned), so we need to have the
 103  * hardware discard the target 0 color output..
 104  */
 105 static void
 106 gen8_emit_null_surface_state(struct brw_context *brw,
 107                              unsigned width,
 108                              unsigned height,
 109                              unsigned samples,
 110                              uint32_t *out_offset)
 111 {
 112    uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
 113
 114    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 115              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 116              GEN8_SURFACE_TILING_Y;
 117    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 118              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 119 }
 120
 121 void
 122 gen8_init_vtable_surface_functions(struct brw_context *brw)
 123 {
 124    brw->vtbl.update_texture_surface = brw_update_texture_surface;
 125    brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
 126    brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
 127    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 128 }