2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/blend.h"
25 #include "main/mtypes.h"
26 #include "main/samplerobj.h"
27 #include "main/texformat.h"
28 #include "main/teximage.h"
29 #include "program/prog_parameter.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_batchbuffer.h"
33 #include "intel_tex.h"
34 #include "intel_fbo.h"
35 #include "intel_buffer_objects.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
43 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
44 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
46 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
49 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
51 * which is simply adding 4 then modding by 8 (or anding with 7).
54 swizzle_to_scs(unsigned swizzle
)
56 return (swizzle
+ 4) & 7;
60 surface_tiling_resource_mode(uint32_t tr_mode
)
63 case INTEL_MIPTREE_TRMODE_YF
:
64 return GEN9_SURFACE_TRMODE_TILEYF
;
65 case INTEL_MIPTREE_TRMODE_YS
:
66 return GEN9_SURFACE_TRMODE_TILEYS
;
68 return GEN9_SURFACE_TRMODE_NONE
;
73 surface_tiling_mode(uint32_t tiling
)
77 return GEN8_SURFACE_TILING_X
;
79 return GEN8_SURFACE_TILING_Y
;
81 return GEN8_SURFACE_TILING_NONE
;
86 vertical_alignment(const struct brw_context
*brw
,
87 const struct intel_mipmap_tree
*mt
,
90 /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
91 * tr_mode is not TRMODE_NONE.
94 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
95 surf_type
== BRW_SURFACE_1D
))
98 switch (mt
->align_h
) {
100 return GEN8_SURFACE_VALIGN_4
;
102 return GEN8_SURFACE_VALIGN_8
;
104 return GEN8_SURFACE_VALIGN_16
;
106 unreachable("Unsupported vertical surface alignment.");
111 horizontal_alignment(const struct brw_context
*brw
,
112 const struct intel_mipmap_tree
*mt
,
115 /* On Gen9+ horizontal alignment is ignored when tr_mode is not
119 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
120 gen9_use_linear_1d_layout(brw
, mt
)))
123 switch (mt
->align_w
) {
125 return GEN8_SURFACE_HALIGN_4
;
127 return GEN8_SURFACE_HALIGN_8
;
129 return GEN8_SURFACE_HALIGN_16
;
131 unreachable("Unsupported horizontal surface alignment.");
136 allocate_surface_state(struct brw_context
*brw
, uint32_t *out_offset
, int index
)
138 int dwords
= brw
->gen
>= 9 ? 16 : 13;
139 uint32_t *surf
= __brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
140 dwords
* 4, 64, index
, out_offset
);
141 memset(surf
, 0, dwords
* 4);
146 gen8_emit_buffer_surface_state(struct brw_context
*brw
,
147 uint32_t *out_offset
,
149 unsigned buffer_offset
,
150 unsigned surface_format
,
151 unsigned buffer_size
,
155 const unsigned mocs
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
156 uint32_t *surf
= allocate_surface_state(brw
, out_offset
, -1);
158 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
159 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
160 BRW_SURFACE_RC_READ_WRITE
;
161 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
);
163 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
164 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
165 if (surface_format
== BRW_SURFACEFORMAT_RAW
)
166 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH
);
168 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
);
169 surf
[3] |= (pitch
- 1);
170 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
171 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
172 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
173 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
175 *((uint64_t *) &surf
[8]) = (bo
? bo
->offset64
: 0) + buffer_offset
;
177 /* Emit relocation to surface contents. */
179 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 8 * 4,
180 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
181 rw
? I915_GEM_DOMAIN_SAMPLER
: 0);
186 gen8_emit_texture_surface_state(struct brw_context
*brw
,
187 struct intel_mipmap_tree
*mt
,
189 unsigned min_layer
, unsigned max_layer
,
190 unsigned min_level
, unsigned max_level
,
193 uint32_t *surf_offset
,
194 bool rw
, bool for_gather
)
196 const unsigned depth
= max_layer
- min_layer
;
197 struct intel_mipmap_tree
*aux_mt
= NULL
;
198 uint32_t aux_mode
= 0;
199 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
200 int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
201 unsigned tiling_mode
, pitch
;
202 const unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
204 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
205 tiling_mode
= GEN8_SURFACE_TILING_W
;
206 pitch
= 2 * mt
->pitch
;
208 tiling_mode
= surface_tiling_mode(mt
->tiling
);
214 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
217 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
218 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
220 * From the hardware spec for GEN9:
221 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
224 assert(brw
->gen
< 9 || mt
->align_w
== 16);
225 assert(brw
->gen
< 8 || mt
->num_samples
> 1 || mt
->align_w
== 16);
228 const uint32_t surf_type
= translate_tex_target(target
);
229 uint32_t *surf
= allocate_surface_state(brw
, surf_offset
, surf_index
);
231 surf
[0] = SET_FIELD(surf_type
, BRW_SURFACE_TYPE
) |
232 format
<< BRW_SURFACE_FORMAT_SHIFT
|
233 vertical_alignment(brw
, mt
, surf_type
) |
234 horizontal_alignment(brw
, mt
, surf_type
) |
237 if (surf_type
== BRW_SURFACE_CUBE
) {
238 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
241 if (_mesa_is_array_texture(target
) || target
== GL_TEXTURE_CUBE_MAP
)
242 surf
[0] |= GEN8_SURFACE_IS_ARRAY
;
244 surf
[1] = SET_FIELD(mocs_wb
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
246 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
247 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
249 surf
[3] = SET_FIELD(depth
- 1, BRW_SURFACE_DEPTH
) | (pitch
- 1);
251 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
) |
252 SET_FIELD(min_layer
, GEN7_SURFACE_MIN_ARRAY_ELEMENT
) |
253 SET_FIELD(depth
- 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT
);
255 surf
[5] = SET_FIELD(min_level
- mt
->first_level
, GEN7_SURFACE_MIN_LOD
) |
256 (max_level
- min_level
- 1); /* mip count */
259 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
260 /* Disable Mip Tail by setting a large value. */
261 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
265 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
266 SET_FIELD((aux_mt
->pitch
/ 128) - 1, GEN8_SURFACE_AUX_PITCH
) |
272 surf
[7] = mt
->fast_clear_color_value
|
273 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 0)), GEN7_SURFACE_SCS_R
) |
274 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 1)), GEN7_SURFACE_SCS_G
) |
275 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 2)), GEN7_SURFACE_SCS_B
) |
276 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 3)), GEN7_SURFACE_SCS_A
);
278 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
281 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
282 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *surf_offset
+ 10 * 4,
284 I915_GEM_DOMAIN_SAMPLER
,
285 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
292 /* Emit relocation to surface contents */
293 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
294 *surf_offset
+ 8 * 4,
297 I915_GEM_DOMAIN_SAMPLER
,
298 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
302 gen8_update_texture_surface(struct gl_context
*ctx
,
304 uint32_t *surf_offset
,
307 struct brw_context
*brw
= brw_context(ctx
);
308 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
310 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
311 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
314 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
315 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
316 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
317 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
318 /* If this is a view with restricted NumLayers, then our effective depth
319 * is not just the miptree depth.
321 const unsigned depth
= (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
?
322 obj
->NumLayers
: mt
->logical_depth0
);
324 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
325 * texturing functions that return a float, as our code generation always
326 * selects the .x channel (which would always be 0).
328 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
329 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
330 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
331 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
332 brw_get_texture_swizzle(&brw
->ctx
, obj
));
334 unsigned format
= translate_tex_format(brw
, intel_obj
->_Format
,
335 sampler
->sRGBDecode
);
336 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
338 format
= BRW_SURFACEFORMAT_R8_UINT
;
341 gen8_emit_texture_surface_state(brw
, mt
, obj
->Target
,
342 obj
->MinLayer
, obj
->MinLayer
+ depth
,
343 obj
->MinLevel
+ obj
->BaseLevel
,
344 obj
->MinLevel
+ intel_obj
->_MaxLevel
+ 1,
345 format
, swizzle
, surf_offset
,
351 * Creates a null surface.
353 * This is used when the shader doesn't write to any color output. An FB
354 * write to target 0 will still be emitted, because that's how the thread is
355 * terminated (and computed depth is returned), so we need to have the
356 * hardware discard the target 0 color output..
359 gen8_emit_null_surface_state(struct brw_context
*brw
,
363 uint32_t *out_offset
)
365 uint32_t *surf
= allocate_surface_state(brw
, out_offset
, -1);
367 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
368 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
369 GEN8_SURFACE_TILING_Y
;
370 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
371 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
375 * Sets up a surface state structure to point at the given region.
376 * While it is only used for the front/back buffer currently, it should be
377 * usable for further buffers when doing ARB_draw_buffer support.
380 gen8_update_renderbuffer_surface(struct brw_context
*brw
,
381 struct gl_renderbuffer
*rb
,
382 bool layered
, unsigned unit
/* unused */,
385 struct gl_context
*ctx
= &brw
->ctx
;
386 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
387 struct intel_mipmap_tree
*mt
= irb
->mt
;
388 struct intel_mipmap_tree
*aux_mt
= NULL
;
389 uint32_t aux_mode
= 0;
390 unsigned width
= mt
->logical_width0
;
391 unsigned height
= mt
->logical_height0
;
392 unsigned pitch
= mt
->pitch
;
393 uint32_t tiling
= mt
->tiling
;
394 unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
398 bool is_array
= false;
399 int depth
= MAX2(irb
->layer_count
, 1);
400 const int min_array_element
= (mt
->format
== MESA_FORMAT_S_UINT8
) ?
401 irb
->mt_layer
: (irb
->mt_layer
/ MAX2(mt
->num_samples
, 1));
403 rb
->TexImage
? rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
404 /* FINISHME: Use PTE MOCS on Skylake. */
405 uint32_t mocs
= brw
->gen
>= 9 ? SKL_MOCS_WT
: BDW_MOCS_PTE
;
407 intel_miptree_used_for_rendering(mt
);
410 case GL_TEXTURE_CUBE_MAP_ARRAY
:
411 case GL_TEXTURE_CUBE_MAP
:
412 surf_type
= BRW_SURFACE_2D
;
417 depth
= MAX2(irb
->mt
->logical_depth0
, 1);
420 surf_type
= translate_tex_target(gl_target
);
421 is_array
= _mesa_tex_target_is_array(gl_target
);
426 /* Render targets can't use IMS layout. Stencil in turn gets configured as
427 * single sampled and indexed manually by the program.
429 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
430 brw_configure_w_tiled(mt
, true, &width
, &height
, &pitch
,
433 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
434 assert(brw_render_target_supported(brw
, rb
));
435 mesa_format rb_format
= _mesa_get_render_format(ctx
,
436 intel_rb_format(irb
));
437 format
= brw
->render_target_format
[rb_format
];
438 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
]))
439 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
440 __func__
, _mesa_get_format_name(rb_format
));
445 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
448 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
449 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
451 * From the hardware spec for GEN9:
452 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
455 assert(brw
->gen
< 9 || mt
->align_w
== 16);
456 assert(brw
->gen
< 8 || mt
->num_samples
> 1 || mt
->align_w
== 16);
459 uint32_t *surf
= allocate_surface_state(brw
, &offset
, surf_index
);
461 surf
[0] = (surf_type
<< BRW_SURFACE_TYPE_SHIFT
) |
462 (is_array
? GEN7_SURFACE_IS_ARRAY
: 0) |
463 (format
<< BRW_SURFACE_FORMAT_SHIFT
) |
464 vertical_alignment(brw
, mt
, surf_type
) |
465 horizontal_alignment(brw
, mt
, surf_type
) |
466 surface_tiling_mode(tiling
);
468 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
470 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
471 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
473 surf
[3] = (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
474 (pitch
- 1); /* Surface Pitch */
476 surf
[4] = min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
477 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
479 if (mt
->format
!= MESA_FORMAT_S_UINT8
)
480 surf
[4] |= gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
482 surf
[5] = irb
->mt_level
- irb
->mt
->first_level
;
485 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
486 /* Disable Mip Tail by setting a large value. */
487 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
491 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
492 SET_FIELD((aux_mt
->pitch
/ 128) - 1, GEN8_SURFACE_AUX_PITCH
) |
498 surf
[7] = mt
->fast_clear_color_value
|
499 SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
500 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
501 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
502 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
504 assert(mt
->offset
% mt
->cpp
== 0);
505 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
508 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
509 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
512 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
519 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
523 I915_GEM_DOMAIN_RENDER
,
524 I915_GEM_DOMAIN_RENDER
);
530 gen8_init_vtable_surface_functions(struct brw_context
*brw
)
532 brw
->vtbl
.update_texture_surface
= gen8_update_texture_surface
;
533 brw
->vtbl
.update_renderbuffer_surface
= gen8_update_renderbuffer_surface
;
534 brw
->vtbl
.emit_null_surface_state
= gen8_emit_null_surface_state
;
535 brw
->vtbl
.emit_texture_surface_state
= gen8_emit_texture_surface_state
;
536 brw
->vtbl
.emit_buffer_surface_state
= gen8_emit_buffer_surface_state
;