2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/blend.h"
25 #include "main/mtypes.h"
26 #include "main/samplerobj.h"
27 #include "main/texformat.h"
28 #include "main/teximage.h"
29 #include "program/prog_parameter.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_batchbuffer.h"
33 #include "intel_tex.h"
34 #include "intel_fbo.h"
35 #include "intel_buffer_objects.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
43 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
44 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
46 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
49 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
51 * which is simply adding 4 then modding by 8 (or anding with 7).
54 swizzle_to_scs(unsigned swizzle
)
56 return (swizzle
+ 4) & 7;
60 surface_tiling_resource_mode(uint32_t tr_mode
)
63 case INTEL_MIPTREE_TRMODE_YF
:
64 return GEN9_SURFACE_TRMODE_TILEYF
;
65 case INTEL_MIPTREE_TRMODE_YS
:
66 return GEN9_SURFACE_TRMODE_TILEYS
;
68 return GEN9_SURFACE_TRMODE_NONE
;
73 surface_tiling_mode(uint32_t tiling
)
77 return GEN8_SURFACE_TILING_X
;
79 return GEN8_SURFACE_TILING_Y
;
81 return GEN8_SURFACE_TILING_NONE
;
86 vertical_alignment(const struct brw_context
*brw
,
87 const struct intel_mipmap_tree
*mt
,
90 /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
91 * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
94 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
95 surf_type
== BRW_SURFACE_1D
))
96 return GEN8_SURFACE_VALIGN_4
;
100 return GEN8_SURFACE_VALIGN_4
;
102 return GEN8_SURFACE_VALIGN_8
;
104 return GEN8_SURFACE_VALIGN_16
;
106 unreachable("Unsupported vertical surface alignment.");
111 horizontal_alignment(const struct brw_context
*brw
,
112 const struct intel_mipmap_tree
*mt
,
115 /* On Gen9+ horizontal alignment is ignored when tr_mode is not
116 * TRMODE_NONE. Set to an arbitrary non-reserved value.
119 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
120 gen9_use_linear_1d_layout(brw
, mt
)))
121 return GEN8_SURFACE_HALIGN_4
;
123 switch (mt
->halign
) {
125 return GEN8_SURFACE_HALIGN_4
;
127 return GEN8_SURFACE_HALIGN_8
;
129 return GEN8_SURFACE_HALIGN_16
;
131 unreachable("Unsupported horizontal surface alignment.");
136 allocate_surface_state(struct brw_context
*brw
, uint32_t *out_offset
, int index
)
138 int dwords
= brw
->gen
>= 9 ? 16 : 13;
139 uint32_t *surf
= __brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
140 dwords
* 4, 64, index
, out_offset
);
141 memset(surf
, 0, dwords
* 4);
146 gen8_emit_buffer_surface_state(struct brw_context
*brw
,
147 uint32_t *out_offset
,
149 unsigned buffer_offset
,
150 unsigned surface_format
,
151 unsigned buffer_size
,
155 const unsigned mocs
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
156 uint32_t *surf
= allocate_surface_state(brw
, out_offset
, -1);
158 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
159 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
160 BRW_SURFACE_RC_READ_WRITE
;
161 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
);
163 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
164 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
165 if (surface_format
== BRW_SURFACEFORMAT_RAW
)
166 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH
);
168 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
);
169 surf
[3] |= (pitch
- 1);
170 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
171 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
172 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
173 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
175 *((uint64_t *) &surf
[8]) = (bo
? bo
->offset64
: 0) + buffer_offset
;
177 /* Emit relocation to surface contents. */
179 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 8 * 4,
180 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
181 rw
? I915_GEM_DOMAIN_SAMPLER
: 0);
186 gen8_emit_fast_clear_color(struct brw_context
*brw
,
187 struct intel_mipmap_tree
*mt
,
190 surf
[7] |= mt
->fast_clear_color_value
;
194 gen8_emit_texture_surface_state(struct brw_context
*brw
,
195 struct intel_mipmap_tree
*mt
,
197 unsigned min_layer
, unsigned max_layer
,
198 unsigned min_level
, unsigned max_level
,
201 uint32_t *surf_offset
,
202 bool rw
, bool for_gather
)
204 const unsigned depth
= max_layer
- min_layer
;
205 struct intel_mipmap_tree
*aux_mt
= NULL
;
206 uint32_t aux_mode
= 0;
207 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
208 int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
209 unsigned tiling_mode
, pitch
;
210 const unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
212 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
213 tiling_mode
= GEN8_SURFACE_TILING_W
;
214 pitch
= 2 * mt
->pitch
;
216 tiling_mode
= surface_tiling_mode(mt
->tiling
);
222 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
225 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
226 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
228 * From the hardware spec for GEN9:
229 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
232 if (brw
->gen
>= 9 || mt
->num_samples
== 1)
233 assert(mt
->halign
== 16);
236 const uint32_t surf_type
= translate_tex_target(target
);
237 uint32_t *surf
= allocate_surface_state(brw
, surf_offset
, surf_index
);
239 surf
[0] = SET_FIELD(surf_type
, BRW_SURFACE_TYPE
) |
240 format
<< BRW_SURFACE_FORMAT_SHIFT
|
241 vertical_alignment(brw
, mt
, surf_type
) |
242 horizontal_alignment(brw
, mt
, surf_type
) |
245 if (surf_type
== BRW_SURFACE_CUBE
) {
246 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
249 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
250 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
252 * This bit must be set for the following surface types: BC2_UNORM
253 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
255 if ((brw
->gen
>= 9 || brw
->is_cherryview
) &&
256 (format
== BRW_SURFACEFORMAT_BC2_UNORM
||
257 format
== BRW_SURFACEFORMAT_BC3_UNORM
||
258 format
== BRW_SURFACEFORMAT_BC5_UNORM
||
259 format
== BRW_SURFACEFORMAT_BC5_SNORM
||
260 format
== BRW_SURFACEFORMAT_BC7_UNORM
))
261 surf
[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE
;
263 if (_mesa_is_array_texture(target
) || target
== GL_TEXTURE_CUBE_MAP
)
264 surf
[0] |= GEN8_SURFACE_IS_ARRAY
;
266 surf
[1] = SET_FIELD(mocs_wb
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
268 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
269 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
271 surf
[3] = SET_FIELD(depth
- 1, BRW_SURFACE_DEPTH
) | (pitch
- 1);
273 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
) |
274 SET_FIELD(min_layer
, GEN7_SURFACE_MIN_ARRAY_ELEMENT
) |
275 SET_FIELD(depth
- 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT
);
277 surf
[5] = SET_FIELD(min_level
- mt
->first_level
, GEN7_SURFACE_MIN_LOD
) |
278 (max_level
- min_level
- 1); /* mip count */
281 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
282 /* Disable Mip Tail by setting a large value. */
283 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
287 uint32_t tile_w
, tile_h
;
288 assert(aux_mt
->tiling
== I915_TILING_Y
);
289 intel_get_tile_dims(aux_mt
->tiling
, aux_mt
->tr_mode
,
290 aux_mt
->cpp
, &tile_w
, &tile_h
);
291 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
292 SET_FIELD((aux_mt
->pitch
/ tile_w
) - 1,
293 GEN8_SURFACE_AUX_PITCH
) |
297 gen8_emit_fast_clear_color(brw
, mt
, surf
);
299 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 0)), GEN7_SURFACE_SCS_R
) |
300 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 1)), GEN7_SURFACE_SCS_G
) |
301 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 2)), GEN7_SURFACE_SCS_B
) |
302 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 3)), GEN7_SURFACE_SCS_A
);
304 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
307 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
308 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *surf_offset
+ 10 * 4,
310 I915_GEM_DOMAIN_SAMPLER
,
311 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
314 /* Emit relocation to surface contents */
315 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
316 *surf_offset
+ 8 * 4,
319 I915_GEM_DOMAIN_SAMPLER
,
320 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
324 gen8_update_texture_surface(struct gl_context
*ctx
,
326 uint32_t *surf_offset
,
329 struct brw_context
*brw
= brw_context(ctx
);
330 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
332 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
333 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
336 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
337 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
338 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
339 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
340 /* If this is a view with restricted NumLayers, then our effective depth
341 * is not just the miptree depth.
343 const unsigned depth
= (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
?
344 obj
->NumLayers
: mt
->logical_depth0
);
346 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
347 * texturing functions that return a float, as our code generation always
348 * selects the .x channel (which would always be 0).
350 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
351 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
352 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
353 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
354 brw_get_texture_swizzle(&brw
->ctx
, obj
));
356 unsigned format
= translate_tex_format(brw
, intel_obj
->_Format
,
357 sampler
->sRGBDecode
);
358 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
360 format
= BRW_SURFACEFORMAT_R8_UINT
;
363 gen8_emit_texture_surface_state(brw
, mt
, obj
->Target
,
364 obj
->MinLayer
, obj
->MinLayer
+ depth
,
365 obj
->MinLevel
+ obj
->BaseLevel
,
366 obj
->MinLevel
+ intel_obj
->_MaxLevel
+ 1,
367 format
, swizzle
, surf_offset
,
373 * Creates a null surface.
375 * This is used when the shader doesn't write to any color output. An FB
376 * write to target 0 will still be emitted, because that's how the thread is
377 * terminated (and computed depth is returned), so we need to have the
378 * hardware discard the target 0 color output..
381 gen8_emit_null_surface_state(struct brw_context
*brw
,
385 uint32_t *out_offset
)
387 uint32_t *surf
= allocate_surface_state(brw
, out_offset
, -1);
389 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
390 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
391 GEN8_SURFACE_TILING_Y
;
392 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
393 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
397 * Sets up a surface state structure to point at the given region.
398 * While it is only used for the front/back buffer currently, it should be
399 * usable for further buffers when doing ARB_draw_buffer support.
402 gen8_update_renderbuffer_surface(struct brw_context
*brw
,
403 struct gl_renderbuffer
*rb
,
404 bool layered
, unsigned unit
/* unused */,
407 struct gl_context
*ctx
= &brw
->ctx
;
408 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
409 struct intel_mipmap_tree
*mt
= irb
->mt
;
410 struct intel_mipmap_tree
*aux_mt
= NULL
;
411 uint32_t aux_mode
= 0;
412 unsigned width
= mt
->logical_width0
;
413 unsigned height
= mt
->logical_height0
;
414 unsigned pitch
= mt
->pitch
;
415 uint32_t tiling
= mt
->tiling
;
416 unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
420 bool is_array
= false;
421 int depth
= MAX2(irb
->layer_count
, 1);
422 const int min_array_element
= (mt
->format
== MESA_FORMAT_S_UINT8
) ?
423 irb
->mt_layer
: (irb
->mt_layer
/ MAX2(mt
->num_samples
, 1));
425 rb
->TexImage
? rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
426 const uint32_t mocs
= brw
->gen
>= 9 ? SKL_MOCS_PTE
: BDW_MOCS_PTE
;
428 intel_miptree_used_for_rendering(mt
);
431 case GL_TEXTURE_CUBE_MAP_ARRAY
:
432 case GL_TEXTURE_CUBE_MAP
:
433 surf_type
= BRW_SURFACE_2D
;
438 depth
= MAX2(irb
->mt
->logical_depth0
, 1);
441 surf_type
= translate_tex_target(gl_target
);
442 is_array
= _mesa_tex_target_is_array(gl_target
);
447 /* Render targets can't use IMS layout. Stencil in turn gets configured as
448 * single sampled and indexed manually by the program.
450 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
451 brw_configure_w_tiled(mt
, true, &width
, &height
, &pitch
,
454 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
455 assert(brw_render_target_supported(brw
, rb
));
456 mesa_format rb_format
= _mesa_get_render_format(ctx
,
457 intel_rb_format(irb
));
458 format
= brw
->render_target_format
[rb_format
];
459 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
]))
460 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
461 __func__
, _mesa_get_format_name(rb_format
));
466 aux_mode
= GEN8_SURFACE_AUX_MODE_MCS
;
469 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
470 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
472 * From the hardware spec for GEN9:
473 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
476 if (brw
->gen
>= 9 || mt
->num_samples
== 1)
477 assert(mt
->halign
== 16);
480 uint32_t *surf
= allocate_surface_state(brw
, &offset
, surf_index
);
482 surf
[0] = (surf_type
<< BRW_SURFACE_TYPE_SHIFT
) |
483 (is_array
? GEN7_SURFACE_IS_ARRAY
: 0) |
484 (format
<< BRW_SURFACE_FORMAT_SHIFT
) |
485 vertical_alignment(brw
, mt
, surf_type
) |
486 horizontal_alignment(brw
, mt
, surf_type
) |
487 surface_tiling_mode(tiling
);
489 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
491 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
492 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
494 surf
[3] = (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
495 (pitch
- 1); /* Surface Pitch */
497 surf
[4] = min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
498 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
500 if (mt
->format
!= MESA_FORMAT_S_UINT8
)
501 surf
[4] |= gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
503 surf
[5] = irb
->mt_level
- irb
->mt
->first_level
;
506 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
507 /* Disable Mip Tail by setting a large value. */
508 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
512 uint32_t tile_w
, tile_h
;
513 assert(aux_mt
->tiling
== I915_TILING_Y
);
514 intel_get_tile_dims(aux_mt
->tiling
, aux_mt
->tr_mode
,
515 aux_mt
->cpp
, &tile_w
, &tile_h
);
516 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
517 SET_FIELD((aux_mt
->pitch
/ tile_w
) - 1,
518 GEN8_SURFACE_AUX_PITCH
) |
522 gen8_emit_fast_clear_color(brw
, mt
, surf
);
523 surf
[7] |= SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
524 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
525 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
526 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
528 assert(mt
->offset
% mt
->cpp
== 0);
529 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
532 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
533 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
536 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
539 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
543 I915_GEM_DOMAIN_RENDER
,
544 I915_GEM_DOMAIN_RENDER
);
550 gen8_init_vtable_surface_functions(struct brw_context
*brw
)
552 brw
->vtbl
.update_texture_surface
= gen8_update_texture_surface
;
553 brw
->vtbl
.update_renderbuffer_surface
= gen8_update_renderbuffer_surface
;
554 brw
->vtbl
.emit_null_surface_state
= gen8_emit_null_surface_state
;
555 brw
->vtbl
.emit_texture_surface_state
= gen8_emit_texture_surface_state
;
556 brw
->vtbl
.emit_buffer_surface_state
= gen8_emit_buffer_surface_state
;