2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/blend.h"
25 #include "main/mtypes.h"
26 #include "main/samplerobj.h"
27 #include "main/texformat.h"
28 #include "program/prog_parameter.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_batchbuffer.h"
32 #include "intel_tex.h"
33 #include "intel_fbo.h"
34 #include "intel_buffer_objects.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38 #include "brw_defines.h"
42 surface_tiling_mode(uint32_t tiling
)
46 return GEN8_SURFACE_TILING_X
;
48 return GEN8_SURFACE_TILING_Y
;
50 return GEN8_SURFACE_TILING_NONE
;
55 vertical_alignment(struct intel_mipmap_tree
*mt
)
57 switch (mt
->align_h
) {
59 return GEN8_SURFACE_VALIGN_4
;
61 return GEN8_SURFACE_VALIGN_8
;
63 return GEN8_SURFACE_VALIGN_16
;
65 assert(!"Unsupported vertical surface alignment.");
66 return GEN8_SURFACE_VALIGN_4
;
71 horizontal_alignment(struct intel_mipmap_tree
*mt
)
73 switch (mt
->align_w
) {
75 return GEN8_SURFACE_HALIGN_4
;
77 return GEN8_SURFACE_HALIGN_8
;
79 return GEN8_SURFACE_HALIGN_16
;
81 assert(!"Unsupported horizontal surface alignment.");
82 return GEN8_SURFACE_HALIGN_4
;
87 gen8_emit_buffer_surface_state(struct brw_context
*brw
,
90 unsigned buffer_offset
,
91 unsigned surface_format
,
97 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
98 13 * 4, 64, out_offset
);
99 memset(surf
, 0, 13 * 4);
101 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
102 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
103 BRW_SURFACE_RC_READ_WRITE
;
104 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
);
106 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
107 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
108 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
) |
110 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
111 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
112 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
113 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
115 *((uint64_t *) &surf
[8]) = (bo
? bo
->offset64
: 0) + buffer_offset
;
117 /* Emit relocation to surface contents. */
119 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 8 * 4,
120 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
121 rw
? I915_GEM_DOMAIN_SAMPLER
: 0);
126 gen8_update_texture_surface(struct gl_context
*ctx
,
128 uint32_t *surf_offset
,
131 struct brw_context
*brw
= brw_context(ctx
);
132 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
133 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
134 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
135 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
136 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
137 mesa_format format
= intelObj
->_Format
;
139 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
140 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
144 if (tObj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
146 format
= MESA_FORMAT_S_UINT8
;
149 unsigned tiling_mode
, pitch
;
150 if (format
== MESA_FORMAT_S_UINT8
) {
151 tiling_mode
= GEN8_SURFACE_TILING_W
;
152 pitch
= 2 * mt
->pitch
;
154 tiling_mode
= surface_tiling_mode(mt
->tiling
);
158 /* If this is a view with restricted NumLayers, then our effective depth
159 * is not just the miptree depth.
161 uint32_t effective_depth
=
162 (tObj
->Immutable
&& tObj
->Target
!= GL_TEXTURE_3D
) ? tObj
->NumLayers
163 : mt
->logical_depth0
;
165 uint32_t tex_format
= translate_tex_format(brw
, format
, sampler
->sRGBDecode
);
167 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
168 13 * 4, 64, surf_offset
);
170 surf
[0] = translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
171 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
|
172 vertical_alignment(mt
) |
173 horizontal_alignment(mt
) |
176 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
||
177 tObj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
) {
178 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
181 if (mt
->logical_depth0
> 1 && tObj
->Target
!= GL_TEXTURE_3D
)
182 surf
[0] |= GEN8_SURFACE_IS_ARRAY
;
184 surf
[1] = SET_FIELD(BDW_MOCS_WB
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
186 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
187 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
189 surf
[3] = SET_FIELD(effective_depth
- 1, BRW_SURFACE_DEPTH
) | (pitch
- 1);
191 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
) |
192 SET_FIELD(tObj
->MinLayer
, GEN7_SURFACE_MIN_ARRAY_ELEMENT
) |
193 SET_FIELD(effective_depth
- 1,
194 GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT
);
196 surf
[5] = SET_FIELD(tObj
->MinLevel
+ tObj
->BaseLevel
- mt
->first_level
,
197 GEN7_SURFACE_MIN_LOD
) |
198 (intelObj
->_MaxLevel
- tObj
->BaseLevel
); /* mip count */
202 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
203 * texturing functions that return a float, as our code generation always
204 * selects the .x channel (which would always be 0).
206 const bool alpha_depth
= tObj
->DepthMode
== GL_ALPHA
&&
207 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
208 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
210 surf
[7] = mt
->fast_clear_color_value
;
213 unlikely(alpha_depth
) ? SWIZZLE_XYZW
: brw_get_texture_swizzle(ctx
, tObj
);
215 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 0), false), GEN7_SURFACE_SCS_R
) |
216 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 1), false), GEN7_SURFACE_SCS_G
) |
217 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 2), false), GEN7_SURFACE_SCS_B
) |
218 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 3), false), GEN7_SURFACE_SCS_A
);
220 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
226 /* Emit relocation to surface contents */
227 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
228 *surf_offset
+ 8 * 4,
231 I915_GEM_DOMAIN_SAMPLER
, 0);
235 gen8_create_raw_surface(struct brw_context
*brw
, drm_intel_bo
*bo
,
236 uint32_t offset
, uint32_t size
,
237 uint32_t *out_offset
, bool rw
)
239 gen8_emit_buffer_surface_state(brw
,
243 BRW_SURFACEFORMAT_RAW
,
251 * Create the constant buffer surface. Vertex/fragment shader constants will be
252 * read from this buffer with Data Port Read instructions/messages.
255 gen8_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned unit
)
257 struct gl_context
*ctx
= &brw
->ctx
;
260 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
261 uint32_t surf_index
=
262 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
264 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 13 * 4, 64,
265 &brw
->wm
.base
.surf_offset
[surf_index
]);
266 memset(surf
, 0, 13 * 4);
268 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
269 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
270 GEN8_SURFACE_TILING_Y
;
271 surf
[2] = SET_FIELD(fb
->Width
- 1, GEN7_SURFACE_WIDTH
) |
272 SET_FIELD(fb
->Height
- 1, GEN7_SURFACE_HEIGHT
);
276 * Sets up a surface state structure to point at the given region.
277 * While it is only used for the front/back buffer currently, it should be
278 * usable for further buffers when doing ARB_draw_buffer support.
281 gen8_update_renderbuffer_surface(struct brw_context
*brw
,
282 struct gl_renderbuffer
*rb
,
286 struct gl_context
*ctx
= &brw
->ctx
;
287 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
288 struct intel_mipmap_tree
*mt
= irb
->mt
;
289 unsigned width
= mt
->logical_width0
;
290 unsigned height
= mt
->logical_height0
;
291 unsigned pitch
= mt
->pitch
;
292 uint32_t tiling
= mt
->tiling
;
295 bool is_array
= false;
296 int depth
= MAX2(irb
->layer_count
, 1);
297 const int min_array_element
= (mt
->format
== MESA_FORMAT_S_UINT8
) ?
298 irb
->mt_layer
: (irb
->mt_layer
/ MAX2(mt
->num_samples
, 1));
300 rb
->TexImage
? rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
302 uint32_t surf_index
=
303 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
305 intel_miptree_used_for_rendering(mt
);
308 case GL_TEXTURE_CUBE_MAP_ARRAY
:
309 case GL_TEXTURE_CUBE_MAP
:
310 surf_type
= BRW_SURFACE_2D
;
315 depth
= MAX2(irb
->mt
->logical_depth0
, 1);
318 surf_type
= translate_tex_target(gl_target
);
319 is_array
= _mesa_tex_target_is_array(gl_target
);
324 /* Render targets can't use IMS layout. Stencil in turn gets configured as
325 * single sampled and indexed manually by the program.
327 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
328 brw_configure_w_tiled(mt
, true, &width
, &height
, &pitch
,
331 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
332 assert(brw_render_target_supported(brw
, rb
));
333 mesa_format rb_format
= _mesa_get_render_format(ctx
,
334 intel_rb_format(irb
));
335 format
= brw
->render_target_format
[rb_format
];
336 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
]))
337 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
338 __FUNCTION__
, _mesa_get_format_name(rb_format
));
341 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 13 * 4, 64,
342 &brw
->wm
.base
.surf_offset
[surf_index
]);
344 surf
[0] = (surf_type
<< BRW_SURFACE_TYPE_SHIFT
) |
345 (is_array
? GEN7_SURFACE_IS_ARRAY
: 0) |
346 (format
<< BRW_SURFACE_FORMAT_SHIFT
) |
347 vertical_alignment(mt
) |
348 horizontal_alignment(mt
) |
349 surface_tiling_mode(tiling
);
351 surf
[1] = SET_FIELD(BDW_MOCS_WT
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
353 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
354 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
356 surf
[3] = (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
357 (pitch
- 1); /* Surface Pitch */
359 surf
[4] = min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
360 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
362 if (mt
->format
!= MESA_FORMAT_S_UINT8
)
363 surf
[4] |= gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
365 surf
[5] = irb
->mt_level
- irb
->mt
->first_level
;
367 surf
[6] = 0; /* Nothing of relevance. */
369 surf
[7] = mt
->fast_clear_color_value
|
370 SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
371 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
372 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
373 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
375 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
; /* reloc */
377 /* Nothing of relevance. */
382 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
383 brw
->wm
.base
.surf_offset
[surf_index
] + 8 * 4,
386 I915_GEM_DOMAIN_RENDER
,
387 I915_GEM_DOMAIN_RENDER
);
391 gen8_init_vtable_surface_functions(struct brw_context
*brw
)
393 brw
->vtbl
.update_texture_surface
= gen8_update_texture_surface
;
394 brw
->vtbl
.update_renderbuffer_surface
= gen8_update_renderbuffer_surface
;
395 brw
->vtbl
.update_null_renderbuffer_surface
=
396 gen8_update_null_renderbuffer_surface
;
397 brw
->vtbl
.create_raw_surface
= gen8_create_raw_surface
;
398 brw
->vtbl
.emit_buffer_surface_state
= gen8_emit_buffer_surface_state
;