2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/blend.h"
25 #include "main/mtypes.h"
26 #include "main/samplerobj.h"
27 #include "main/texformat.h"
28 #include "main/teximage.h"
29 #include "program/prog_parameter.h"
30 #include "program/prog_instruction.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_batchbuffer.h"
34 #include "intel_tex.h"
35 #include "intel_fbo.h"
36 #include "intel_buffer_objects.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
44 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
45 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
47 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
50 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
52 * which is simply adding 4 then modding by 8 (or anding with 7).
55 swizzle_to_scs(unsigned swizzle
)
57 return (swizzle
+ 4) & 7;
61 surface_tiling_resource_mode(uint32_t tr_mode
)
64 case INTEL_MIPTREE_TRMODE_YF
:
65 return GEN9_SURFACE_TRMODE_TILEYF
;
66 case INTEL_MIPTREE_TRMODE_YS
:
67 return GEN9_SURFACE_TRMODE_TILEYS
;
69 return GEN9_SURFACE_TRMODE_NONE
;
74 gen8_surface_tiling_mode(uint32_t tiling
)
78 return GEN8_SURFACE_TILING_X
;
80 return GEN8_SURFACE_TILING_Y
;
82 return GEN8_SURFACE_TILING_NONE
;
87 gen8_vertical_alignment(const struct brw_context
*brw
,
88 const struct intel_mipmap_tree
*mt
,
91 /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
92 * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
95 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
96 surf_type
== BRW_SURFACE_1D
))
97 return GEN8_SURFACE_VALIGN_4
;
101 return GEN8_SURFACE_VALIGN_4
;
103 return GEN8_SURFACE_VALIGN_8
;
105 return GEN8_SURFACE_VALIGN_16
;
107 unreachable("Unsupported vertical surface alignment.");
112 gen8_horizontal_alignment(const struct brw_context
*brw
,
113 const struct intel_mipmap_tree
*mt
,
116 /* On Gen9+ horizontal alignment is ignored when tr_mode is not
117 * TRMODE_NONE. Set to an arbitrary non-reserved value.
120 (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
121 gen9_use_linear_1d_layout(brw
, mt
)))
122 return GEN8_SURFACE_HALIGN_4
;
124 switch (mt
->halign
) {
126 return GEN8_SURFACE_HALIGN_4
;
128 return GEN8_SURFACE_HALIGN_8
;
130 return GEN8_SURFACE_HALIGN_16
;
132 unreachable("Unsupported horizontal surface alignment.");
137 gen8_allocate_surface_state(struct brw_context
*brw
,
138 uint32_t *out_offset
, int index
)
140 int dwords
= brw
->gen
>= 9 ? 16 : 13;
141 uint32_t *surf
= __brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
142 dwords
* 4, 64, index
, out_offset
);
143 memset(surf
, 0, dwords
* 4);
148 gen8_emit_buffer_surface_state(struct brw_context
*brw
,
149 uint32_t *out_offset
,
151 unsigned buffer_offset
,
152 unsigned surface_format
,
153 unsigned buffer_size
,
157 const unsigned mocs
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
158 uint32_t *surf
= gen8_allocate_surface_state(brw
, out_offset
, -1);
160 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
161 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
162 BRW_SURFACE_RC_READ_WRITE
;
163 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
);
165 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
166 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
167 if (surface_format
== BRW_SURFACEFORMAT_RAW
)
168 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH
);
170 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
);
171 surf
[3] |= (pitch
- 1);
172 surf
[7] = SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
173 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
174 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
175 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
177 *((uint64_t *) &surf
[8]) = (bo
? bo
->offset64
: 0) + buffer_offset
;
179 /* Emit relocation to surface contents. */
181 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 8 * 4,
182 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
183 rw
? I915_GEM_DOMAIN_SAMPLER
: 0);
188 gen8_emit_fast_clear_color(const struct brw_context
*brw
,
189 const struct intel_mipmap_tree
*mt
,
193 surf
[12] = mt
->gen9_fast_clear_color
.ui
[0];
194 surf
[13] = mt
->gen9_fast_clear_color
.ui
[1];
195 surf
[14] = mt
->gen9_fast_clear_color
.ui
[2];
196 surf
[15] = mt
->gen9_fast_clear_color
.ui
[3];
198 surf
[7] |= mt
->fast_clear_color_value
;
202 gen8_get_aux_mode(const struct brw_context
*brw
,
203 const struct intel_mipmap_tree
*mt
)
205 if (mt
->mcs_mt
== NULL
)
206 return GEN8_SURFACE_AUX_MODE_NONE
;
209 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
210 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
212 * From the hardware spec for GEN9:
213 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
216 if (brw
->gen
>= 9 || mt
->num_samples
== 1)
217 assert(mt
->halign
== 16);
219 return GEN8_SURFACE_AUX_MODE_MCS
;
223 gen8_emit_texture_surface_state(struct brw_context
*brw
,
224 struct intel_mipmap_tree
*mt
,
226 unsigned min_layer
, unsigned max_layer
,
227 unsigned min_level
, unsigned max_level
,
230 uint32_t *surf_offset
, int surf_index
,
231 bool rw
, bool for_gather
)
233 const unsigned depth
= max_layer
- min_layer
;
234 struct intel_mipmap_tree
*aux_mt
= mt
->mcs_mt
;
235 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
236 unsigned tiling_mode
, pitch
;
237 const unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
238 const uint32_t surf_type
= translate_tex_target(target
);
239 uint32_t aux_mode
= gen8_get_aux_mode(brw
, mt
);
241 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
242 tiling_mode
= GEN8_SURFACE_TILING_W
;
243 pitch
= 2 * mt
->pitch
;
245 tiling_mode
= gen8_surface_tiling_mode(mt
->tiling
);
249 /* The MCS is not uploaded for single-sampled surfaces because the color
250 * buffer should always have been resolved before it is used as a texture
251 * so there is no need for it.
253 if (mt
->num_samples
<= 1) {
255 aux_mode
= GEN8_SURFACE_AUX_MODE_NONE
;
258 uint32_t *surf
= gen8_allocate_surface_state(brw
, surf_offset
, surf_index
);
260 surf
[0] = SET_FIELD(surf_type
, BRW_SURFACE_TYPE
) |
261 format
<< BRW_SURFACE_FORMAT_SHIFT
|
262 gen8_vertical_alignment(brw
, mt
, surf_type
) |
263 gen8_horizontal_alignment(brw
, mt
, surf_type
) |
266 if (surf_type
== BRW_SURFACE_CUBE
) {
267 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
270 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
271 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
273 * This bit must be set for the following surface types: BC2_UNORM
274 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
276 if ((brw
->gen
>= 9 || brw
->is_cherryview
) &&
277 (format
== BRW_SURFACEFORMAT_BC2_UNORM
||
278 format
== BRW_SURFACEFORMAT_BC3_UNORM
||
279 format
== BRW_SURFACEFORMAT_BC5_UNORM
||
280 format
== BRW_SURFACEFORMAT_BC5_SNORM
||
281 format
== BRW_SURFACEFORMAT_BC7_UNORM
))
282 surf
[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE
;
284 if (_mesa_is_array_texture(mt
->target
) || mt
->target
== GL_TEXTURE_CUBE_MAP
)
285 surf
[0] |= GEN8_SURFACE_IS_ARRAY
;
287 surf
[1] = SET_FIELD(mocs_wb
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
289 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
290 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
292 surf
[3] = SET_FIELD(depth
- 1, BRW_SURFACE_DEPTH
) | (pitch
- 1);
294 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
) |
295 SET_FIELD(min_layer
, GEN7_SURFACE_MIN_ARRAY_ELEMENT
) |
296 SET_FIELD(depth
- 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT
);
298 surf
[5] = SET_FIELD(min_level
- mt
->first_level
, GEN7_SURFACE_MIN_LOD
) |
299 (max_level
- min_level
- 1); /* mip count */
302 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
303 /* Disable Mip Tail by setting a large value. */
304 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
308 uint32_t tile_w
, tile_h
;
309 assert(aux_mt
->tiling
== I915_TILING_Y
);
310 intel_get_tile_dims(aux_mt
->tiling
, aux_mt
->tr_mode
,
311 aux_mt
->cpp
, &tile_w
, &tile_h
);
312 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
313 SET_FIELD((aux_mt
->pitch
/ tile_w
) - 1,
314 GEN8_SURFACE_AUX_PITCH
) |
318 gen8_emit_fast_clear_color(brw
, mt
, surf
);
320 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 0)), GEN7_SURFACE_SCS_R
) |
321 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 1)), GEN7_SURFACE_SCS_G
) |
322 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 2)), GEN7_SURFACE_SCS_B
) |
323 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 3)), GEN7_SURFACE_SCS_A
);
325 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
328 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
329 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *surf_offset
+ 10 * 4,
331 I915_GEM_DOMAIN_SAMPLER
,
332 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
335 /* Emit relocation to surface contents */
336 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
337 *surf_offset
+ 8 * 4,
340 I915_GEM_DOMAIN_SAMPLER
,
341 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
345 gen8_update_texture_surface(struct gl_context
*ctx
,
347 uint32_t *surf_offset
,
350 struct brw_context
*brw
= brw_context(ctx
);
351 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
353 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
354 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
357 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
358 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
359 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
360 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
361 /* If this is a view with restricted NumLayers, then our effective depth
362 * is not just the miptree depth.
364 const unsigned depth
= (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
?
365 obj
->NumLayers
: mt
->logical_depth0
);
367 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
368 * texturing functions that return a float, as our code generation always
369 * selects the .x channel (which would always be 0).
371 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
372 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
373 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
374 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
375 brw_get_texture_swizzle(&brw
->ctx
, obj
));
377 unsigned format
= translate_tex_format(brw
, intel_obj
->_Format
,
378 sampler
->sRGBDecode
);
379 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
381 format
= BRW_SURFACEFORMAT_R8_UINT
;
384 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
386 gen8_emit_texture_surface_state(brw
, mt
, obj
->Target
,
387 obj
->MinLayer
, obj
->MinLayer
+ depth
,
388 obj
->MinLevel
+ obj
->BaseLevel
,
389 obj
->MinLevel
+ intel_obj
->_MaxLevel
+ 1,
390 format
, swizzle
, surf_offset
,
391 surf_index
, false, for_gather
);
396 * Creates a null surface.
398 * This is used when the shader doesn't write to any color output. An FB
399 * write to target 0 will still be emitted, because that's how the thread is
400 * terminated (and computed depth is returned), so we need to have the
401 * hardware discard the target 0 color output..
404 gen8_emit_null_surface_state(struct brw_context
*brw
,
408 uint32_t *out_offset
)
410 uint32_t *surf
= gen8_allocate_surface_state(brw
, out_offset
, -1);
412 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
413 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
414 GEN8_SURFACE_TILING_Y
;
415 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
416 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
420 * Sets up a surface state structure to point at the given region.
421 * While it is only used for the front/back buffer currently, it should be
422 * usable for further buffers when doing ARB_draw_buffer support.
425 gen8_update_renderbuffer_surface(struct brw_context
*brw
,
426 struct gl_renderbuffer
*rb
,
427 bool layered
, unsigned unit
/* unused */,
430 struct gl_context
*ctx
= &brw
->ctx
;
431 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
432 struct intel_mipmap_tree
*mt
= irb
->mt
;
433 unsigned width
= mt
->logical_width0
;
434 unsigned height
= mt
->logical_height0
;
435 unsigned pitch
= mt
->pitch
;
436 uint32_t tiling
= mt
->tiling
;
437 unsigned tr_mode
= surface_tiling_resource_mode(mt
->tr_mode
);
441 bool is_array
= false;
442 int depth
= MAX2(irb
->layer_count
, 1);
443 const int min_array_element
= (mt
->format
== MESA_FORMAT_S_UINT8
) ?
444 irb
->mt_layer
: (irb
->mt_layer
/ MAX2(mt
->num_samples
, 1));
446 rb
->TexImage
? rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
447 const uint32_t mocs
= brw
->gen
>= 9 ? SKL_MOCS_PTE
: BDW_MOCS_PTE
;
449 intel_miptree_used_for_rendering(mt
);
452 case GL_TEXTURE_CUBE_MAP_ARRAY
:
453 case GL_TEXTURE_CUBE_MAP
:
454 surf_type
= BRW_SURFACE_2D
;
459 depth
= MAX2(irb
->mt
->logical_depth0
, 1);
462 surf_type
= translate_tex_target(gl_target
);
463 is_array
= _mesa_is_array_texture(mt
->target
);
468 /* Render targets can't use IMS layout. Stencil in turn gets configured as
469 * single sampled and indexed manually by the program.
471 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
472 brw_configure_w_tiled(mt
, true, &width
, &height
, &pitch
,
475 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
476 assert(brw_render_target_supported(brw
, rb
));
477 mesa_format rb_format
= _mesa_get_render_format(ctx
,
478 intel_rb_format(irb
));
479 format
= brw
->render_target_format
[rb_format
];
480 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
]))
481 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
482 __func__
, _mesa_get_format_name(rb_format
));
485 struct intel_mipmap_tree
*aux_mt
= mt
->mcs_mt
;
486 const uint32_t aux_mode
= gen8_get_aux_mode(brw
, mt
);
488 uint32_t *surf
= gen8_allocate_surface_state(brw
, &offset
, surf_index
);
490 surf
[0] = (surf_type
<< BRW_SURFACE_TYPE_SHIFT
) |
491 (is_array
? GEN7_SURFACE_IS_ARRAY
: 0) |
492 (format
<< BRW_SURFACE_FORMAT_SHIFT
) |
493 gen8_vertical_alignment(brw
, mt
, surf_type
) |
494 gen8_horizontal_alignment(brw
, mt
, surf_type
) |
495 gen8_surface_tiling_mode(tiling
);
497 surf
[1] = SET_FIELD(mocs
, GEN8_SURFACE_MOCS
) | mt
->qpitch
>> 2;
499 surf
[2] = SET_FIELD(width
- 1, GEN7_SURFACE_WIDTH
) |
500 SET_FIELD(height
- 1, GEN7_SURFACE_HEIGHT
);
502 surf
[3] = (depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
|
503 (pitch
- 1); /* Surface Pitch */
505 surf
[4] = min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
506 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
508 if (mt
->format
!= MESA_FORMAT_S_UINT8
)
509 surf
[4] |= gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
511 surf
[5] = irb
->mt_level
- irb
->mt
->first_level
;
514 surf
[5] |= SET_FIELD(tr_mode
, GEN9_SURFACE_TRMODE
);
515 /* Disable Mip Tail by setting a large value. */
516 surf
[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD
);
520 uint32_t tile_w
, tile_h
;
521 assert(aux_mt
->tiling
== I915_TILING_Y
);
522 intel_get_tile_dims(aux_mt
->tiling
, aux_mt
->tr_mode
,
523 aux_mt
->cpp
, &tile_w
, &tile_h
);
524 surf
[6] = SET_FIELD(mt
->qpitch
/ 4, GEN8_SURFACE_AUX_QPITCH
) |
525 SET_FIELD((aux_mt
->pitch
/ tile_w
) - 1,
526 GEN8_SURFACE_AUX_PITCH
) |
530 gen8_emit_fast_clear_color(brw
, mt
, surf
);
531 surf
[7] |= SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
532 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
533 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
534 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
);
536 assert(mt
->offset
% mt
->cpp
== 0);
537 *((uint64_t *) &surf
[8]) = mt
->bo
->offset64
+ mt
->offset
; /* reloc */
540 *((uint64_t *) &surf
[10]) = aux_mt
->bo
->offset64
;
541 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
544 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
547 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
551 I915_GEM_DOMAIN_RENDER
,
552 I915_GEM_DOMAIN_RENDER
);
558 gen8_init_vtable_surface_functions(struct brw_context
*brw
)
560 brw
->vtbl
.update_texture_surface
= gen8_update_texture_surface
;
561 brw
->vtbl
.update_renderbuffer_surface
= gen8_update_renderbuffer_surface
;
562 brw
->vtbl
.emit_null_surface_state
= gen8_emit_null_surface_state
;
563 brw
->vtbl
.emit_texture_surface_state
= gen8_emit_texture_surface_state
;
564 brw
->vtbl
.emit_buffer_surface_state
= gen8_emit_buffer_surface_state
;