src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "program/prog_parameter.h"
  29
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "intel_tex.h"
  33 #include "intel_fbo.h"
  34 #include "intel_buffer_objects.h"
  35
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40
  41 static uint32_t
  42 surface_tiling_mode(uint32_t tiling)
  43 {
  44    switch (tiling) {
  45    case I915_TILING_X:
  46       return GEN8_SURFACE_TILING_X;
  47    case I915_TILING_Y:
  48       return GEN8_SURFACE_TILING_Y;
  49    default:
  50       return GEN8_SURFACE_TILING_NONE;
  51    }
  52 }
  53
  54 static unsigned
  55 vertical_alignment(struct intel_mipmap_tree *mt)
  56 {
  57    switch (mt->align_h) {
  58    case 4:
  59       return GEN8_SURFACE_VALIGN_4;
  60    case 8:
  61       return GEN8_SURFACE_VALIGN_8;
  62    case 16:
  63       return GEN8_SURFACE_VALIGN_16;
  64    default:
  65       unreachable("Unsupported vertical surface alignment.");
  66    }
  67 }
  68
  69 static unsigned
  70 horizontal_alignment(struct intel_mipmap_tree *mt)
  71 {
  72    switch (mt->align_w) {
  73    case 4:
  74       return GEN8_SURFACE_HALIGN_4;
  75    case 8:
  76       return GEN8_SURFACE_HALIGN_8;
  77    case 16:
  78       return GEN8_SURFACE_HALIGN_16;
  79    default:
  80       unreachable("Unsupported horizontal surface alignment.");
  81    }
  82 }
  83
  84 static uint32_t *
  85 allocate_surface_state(struct brw_context *brw, uint32_t *out_offset)
  86 {
  87    int dwords = brw->gen >= 9 ? 16 : 13;
  88    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  89                                     dwords * 4, 64, out_offset);
  90    memset(surf, 0, dwords * 4);
  91    return surf;
  92 }
  93
  94 static void
  95 gen8_emit_buffer_surface_state(struct brw_context *brw,
  96                                uint32_t *out_offset,
  97                                drm_intel_bo *bo,
  98                                unsigned buffer_offset,
  99                                unsigned surface_format,
 100                                unsigned buffer_size,
 101                                unsigned pitch,
 102                                unsigned mocs,
 103                                bool rw)
 104 {
 105    uint32_t *surf = allocate_surface_state(brw, out_offset);
 106
 107    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 108              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 109              BRW_SURFACE_RC_READ_WRITE;
 110    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
 111
 112    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 113              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 114    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 115              (pitch - 1);
 116    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 117              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 118              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 119              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 120    /* reloc */
 121    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 122
 123    /* Emit relocation to surface contents. */
 124    if (bo) {
 125       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 126                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 127                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 128    }
 129 }
 130
 131 static void
 132 gen8_update_texture_surface(struct gl_context *ctx,
 133                             unsigned unit,
 134                             uint32_t *surf_offset,
 135                             bool for_gather)
 136 {
 137    struct brw_context *brw = brw_context(ctx);
 138    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 139    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 140    struct intel_mipmap_tree *mt = intelObj->mt;
 141    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 142    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 143    struct intel_mipmap_tree *aux_mt = NULL;
 144    uint32_t aux_mode = 0;
 145    mesa_format format = intelObj->_Format;
 146    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 147
 148    if (tObj->Target == GL_TEXTURE_BUFFER) {
 149       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 150       return;
 151    }
 152
 153    if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
 154       mt = mt->stencil_mt;
 155       format = MESA_FORMAT_S_UINT8;
 156    }
 157
 158    unsigned tiling_mode, pitch;
 159    if (format == MESA_FORMAT_S_UINT8) {
 160       tiling_mode = GEN8_SURFACE_TILING_W;
 161       pitch = 2 * mt->pitch;
 162    } else {
 163       tiling_mode = surface_tiling_mode(mt->tiling);
 164       pitch = mt->pitch;
 165    }
 166
 167    if (mt->mcs_mt) {
 168       aux_mt = mt->mcs_mt;
 169       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 170    }
 171
 172    /* If this is a view with restricted NumLayers, then our effective depth
 173     * is not just the miptree depth.
 174     */
 175    uint32_t effective_depth =
 176       (tObj->Immutable && tObj->Target != GL_TEXTURE_3D) ? tObj->NumLayers
 177                                                          : mt->logical_depth0;
 178
 179    uint32_t tex_format = translate_tex_format(brw, format, sampler->sRGBDecode);
 180
 181    uint32_t *surf = allocate_surface_state(brw, surf_offset);
 182
 183    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 184              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 185              vertical_alignment(mt) |
 186              horizontal_alignment(mt) |
 187              tiling_mode;
 188
 189    if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
 190        tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
 191       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 192    }
 193
 194    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 195       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 196
 197    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 198
 199    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 200              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 201
 202    surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 203
 204    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 205              SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 206              SET_FIELD(effective_depth - 1,
 207                        GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 208
 209    surf[5] = SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level,
 210                        GEN7_SURFACE_MIN_LOD) |
 211              (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
 212
 213    if (aux_mt) {
 214       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 215                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
 216                 aux_mode;
 217    } else {
 218       surf[6] = 0;
 219    }
 220
 221    /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 222     * texturing functions that return a float, as our code generation always
 223     * selects the .x channel (which would always be 0).
 224     */
 225    const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 226       (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 227        firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 228
 229    surf[7] = mt->fast_clear_color_value;
 230
 231    const int swizzle =
 232       unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 233    surf[7] |=
 234       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), false), GEN7_SURFACE_SCS_R) |
 235       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), false), GEN7_SURFACE_SCS_G) |
 236       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
 237       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
 238
 239    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 240
 241    if (aux_mt) {
 242       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 243       drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
 244                               aux_mt->bo, 0,
 245                               I915_GEM_DOMAIN_SAMPLER, 0);
 246    } else {
 247       surf[10] = 0;
 248       surf[11] = 0;
 249    }
 250    surf[12] = 0;
 251
 252    /* Emit relocation to surface contents */
 253    drm_intel_bo_emit_reloc(brw->batch.bo,
 254                            *surf_offset + 8 * 4,
 255                            mt->bo,
 256                            mt->offset,
 257                            I915_GEM_DOMAIN_SAMPLER, 0);
 258 }
 259
 260 static void
 261 gen8_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
 262                         uint32_t offset, uint32_t size,
 263                         uint32_t *out_offset, bool rw)
 264 {
 265    gen8_emit_buffer_surface_state(brw,
 266                                   out_offset,
 267                                   bo,
 268                                   offset,
 269                                   BRW_SURFACEFORMAT_RAW,
 270                                   size,
 271                                   1,
 272                                   0 /* mocs */,
 273                                   true /* rw */);
 274 }
 275
 276 /**
 277  * Creates a null renderbuffer surface.
 278  *
 279  * This is used when the shader doesn't write to any color output.  An FB
 280  * write to target 0 will still be emitted, because that's how the thread is
 281  * terminated (and computed depth is returned), so we need to have the
 282  * hardware discard the target 0 color output..
 283  */
 284 static void
 285 gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 286 {
 287    struct gl_context *ctx = &brw->ctx;
 288
 289    /* _NEW_BUFFERS */
 290    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 291    uint32_t surf_index =
 292       brw->wm.prog_data->binding_table.render_target_start + unit;
 293
 294    uint32_t *surf =
 295       allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]);
 296
 297    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 298              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 299              GEN8_SURFACE_TILING_Y;
 300    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 301              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 302 }
 303
 304 /**
 305  * Sets up a surface state structure to point at the given region.
 306  * While it is only used for the front/back buffer currently, it should be
 307  * usable for further buffers when doing ARB_draw_buffer support.
 308  */
 309 static void
 310 gen8_update_renderbuffer_surface(struct brw_context *brw,
 311                                  struct gl_renderbuffer *rb,
 312                                  bool layered,
 313                                  unsigned unit)
 314 {
 315    struct gl_context *ctx = &brw->ctx;
 316    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 317    struct intel_mipmap_tree *mt = irb->mt;
 318    struct intel_mipmap_tree *aux_mt = NULL;
 319    uint32_t aux_mode = 0;
 320    unsigned width = mt->logical_width0;
 321    unsigned height = mt->logical_height0;
 322    unsigned pitch = mt->pitch;
 323    uint32_t tiling = mt->tiling;
 324    uint32_t format = 0;
 325    uint32_t surf_type;
 326    bool is_array = false;
 327    int depth = MAX2(irb->layer_count, 1);
 328    const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
 329       irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
 330    GLenum gl_target =
 331       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 332    uint32_t surf_index =
 333       brw->wm.prog_data->binding_table.render_target_start + unit;
 334    /* FINISHME: Use PTE MOCS on Skylake. */
 335    uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
 336
 337    intel_miptree_used_for_rendering(mt);
 338
 339    switch (gl_target) {
 340    case GL_TEXTURE_CUBE_MAP_ARRAY:
 341    case GL_TEXTURE_CUBE_MAP:
 342       surf_type = BRW_SURFACE_2D;
 343       is_array = true;
 344       depth *= 6;
 345       break;
 346    case GL_TEXTURE_3D:
 347       depth = MAX2(irb->mt->logical_depth0, 1);
 348       /* fallthrough */
 349    default:
 350       surf_type = translate_tex_target(gl_target);
 351       is_array = _mesa_tex_target_is_array(gl_target);
 352       break;
 353    }
 354
 355    /* _NEW_BUFFERS */
 356    /* Render targets can't use IMS layout. Stencil in turn gets configured as
 357     * single sampled and indexed manually by the program.
 358     */
 359    if (mt->format == MESA_FORMAT_S_UINT8) {
 360       brw_configure_w_tiled(mt, true, &width, &height, &pitch,
 361                             &tiling, &format);
 362    } else {
 363       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 364       assert(brw_render_target_supported(brw, rb));
 365       mesa_format rb_format = _mesa_get_render_format(ctx,
 366                                                       intel_rb_format(irb));
 367       format = brw->render_target_format[rb_format];
 368       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
 369          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 370                        __FUNCTION__, _mesa_get_format_name(rb_format));
 371    }
 372
 373    if (mt->mcs_mt) {
 374       aux_mt = mt->mcs_mt;
 375       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 376    }
 377
 378    uint32_t *surf =
 379       allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]);
 380
 381    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 382              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 383              (format << BRW_SURFACE_FORMAT_SHIFT) |
 384              vertical_alignment(mt) |
 385              horizontal_alignment(mt) |
 386              surface_tiling_mode(tiling);
 387
 388    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 389
 390    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 391              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 392
 393    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 394              (pitch - 1); /* Surface Pitch */
 395
 396    surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 397              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 398
 399    if (mt->format != MESA_FORMAT_S_UINT8)
 400       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 401
 402    surf[5] = irb->mt_level - irb->mt->first_level;
 403
 404    if (aux_mt) {
 405       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 406                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
 407                 aux_mode;
 408    } else {
 409       surf[6] = 0;
 410    }
 411
 412    surf[7] = mt->fast_clear_color_value |
 413              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 414              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 415              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 416              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 417
 418    *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
 419
 420    if (aux_mt) {
 421       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 422       drm_intel_bo_emit_reloc(brw->batch.bo,
 423                               brw->wm.base.surf_offset[surf_index] + 10 * 4,
 424                               aux_mt->bo, 0,
 425                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 426    } else {
 427       surf[10] = 0;
 428       surf[11] = 0;
 429    }
 430    surf[12] = 0;
 431
 432    drm_intel_bo_emit_reloc(brw->batch.bo,
 433                            brw->wm.base.surf_offset[surf_index] + 8 * 4,
 434                            mt->bo,
 435                            0,
 436                            I915_GEM_DOMAIN_RENDER,
 437                            I915_GEM_DOMAIN_RENDER);
 438 }
 439
 440 void
 441 gen8_init_vtable_surface_functions(struct brw_context *brw)
 442 {
 443    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 444    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 445    brw->vtbl.update_null_renderbuffer_surface =
 446       gen8_update_null_renderbuffer_surface;
 447    brw->vtbl.create_raw_surface = gen8_create_raw_surface;
 448    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 449 }