src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "program/prog_parameter.h"
  29
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "intel_tex.h"
  33 #include "intel_fbo.h"
  34 #include "intel_buffer_objects.h"
  35
  36 #include "brw_context.h"
  37 #include "brw_state.h"
  38 #include "brw_defines.h"
  39 #include "brw_wm.h"
  40
  41 static uint32_t
  42 surface_tiling_mode(uint32_t tiling)
  43 {
  44    switch (tiling) {
  45    case I915_TILING_X:
  46       return GEN8_SURFACE_TILING_X;
  47    case I915_TILING_Y:
  48       return GEN8_SURFACE_TILING_Y;
  49    default:
  50       return GEN8_SURFACE_TILING_NONE;
  51    }
  52 }
  53
  54 static unsigned
  55 vertical_alignment(struct intel_mipmap_tree *mt)
  56 {
  57    switch (mt->align_h) {
  58    case 4:
  59       return GEN8_SURFACE_VALIGN_4;
  60    case 8:
  61       return GEN8_SURFACE_VALIGN_8;
  62    case 16:
  63       return GEN8_SURFACE_VALIGN_16;
  64    default:
  65       assert(!"Unsupported vertical surface alignment.");
  66       return GEN8_SURFACE_VALIGN_4;
  67    }
  68 }
  69
  70 static unsigned
  71 horizontal_alignment(struct intel_mipmap_tree *mt)
  72 {
  73    switch (mt->align_w) {
  74    case 4:
  75       return GEN8_SURFACE_HALIGN_4;
  76    case 8:
  77       return GEN8_SURFACE_HALIGN_8;
  78    case 16:
  79       return GEN8_SURFACE_HALIGN_16;
  80    default:
  81       assert(!"Unsupported horizontal surface alignment.");
  82       return GEN8_SURFACE_HALIGN_4;
  83    }
  84 }
  85
  86 static void
  87 gen8_emit_buffer_surface_state(struct brw_context *brw,
  88                                uint32_t *out_offset,
  89                                drm_intel_bo *bo,
  90                                unsigned buffer_offset,
  91                                unsigned surface_format,
  92                                unsigned buffer_size,
  93                                unsigned pitch,
  94                                unsigned mocs,
  95                                bool rw)
  96 {
  97    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  98                                     13 * 4, 64, out_offset);
  99    memset(surf, 0, 13 * 4);
 100
 101    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 102              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 103              BRW_SURFACE_RC_READ_WRITE;
 104    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
 105
 106    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 107              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 108    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 109              (pitch - 1);
 110    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 111              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 112              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 113              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 114    /* reloc */
 115    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 116
 117    /* Emit relocation to surface contents. */
 118    if (bo) {
 119       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 120                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 121                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 122    }
 123 }
 124
 125 static void
 126 gen8_update_texture_surface(struct gl_context *ctx,
 127                             unsigned unit,
 128                             uint32_t *surf_offset,
 129                             bool for_gather)
 130 {
 131    struct brw_context *brw = brw_context(ctx);
 132    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 133    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 134    struct intel_mipmap_tree *mt = intelObj->mt;
 135    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 136    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 137
 138    if (tObj->Target == GL_TEXTURE_BUFFER) {
 139       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 140       return;
 141    }
 142
 143    if (tObj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL)
 144       mt = mt->stencil_mt;
 145
 146    unsigned tiling_mode, pitch;
 147    if (mt->format == MESA_FORMAT_S_UINT8) {
 148       tiling_mode = GEN8_SURFACE_TILING_W;
 149       pitch = 2 * mt->pitch;
 150    } else {
 151       tiling_mode = surface_tiling_mode(mt->tiling);
 152       pitch = mt->pitch;
 153    }
 154
 155    uint32_t tex_format = translate_tex_format(brw,
 156                                               mt->format,
 157                                               sampler->sRGBDecode);
 158
 159    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 160                                     13 * 4, 64, surf_offset);
 161
 162    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 163              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 164              vertical_alignment(mt) |
 165              horizontal_alignment(mt) |
 166              tiling_mode;
 167
 168    if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
 169        tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
 170       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 171    }
 172
 173    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 174       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 175
 176    surf[1] = SET_FIELD(BDW_MOCS_WB, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 177
 178    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 179              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 180
 181    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 182
 183    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 184
 185    surf[5] = SET_FIELD(tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 186              (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
 187
 188    surf[6] = 0;
 189
 190    /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 191     * texturing functions that return a float, as our code generation always
 192     * selects the .x channel (which would always be 0).
 193     */
 194    const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 195       (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 196        firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 197
 198    const int swizzle =
 199       unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 200    surf[7] =
 201       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), false), GEN7_SURFACE_SCS_R) |
 202       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), false), GEN7_SURFACE_SCS_G) |
 203       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), false), GEN7_SURFACE_SCS_B) |
 204       SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), false), GEN7_SURFACE_SCS_A);
 205
 206    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 207
 208    surf[10] = 0;
 209    surf[11] = 0;
 210    surf[12] = 0;
 211
 212    /* Emit relocation to surface contents */
 213    drm_intel_bo_emit_reloc(brw->batch.bo,
 214                            *surf_offset + 8 * 4,
 215                            mt->bo,
 216                            mt->offset,
 217                            I915_GEM_DOMAIN_SAMPLER, 0);
 218 }
 219
 220 static void
 221 gen8_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
 222                         uint32_t offset, uint32_t size,
 223                         uint32_t *out_offset, bool rw)
 224 {
 225    gen8_emit_buffer_surface_state(brw,
 226                                   out_offset,
 227                                   bo,
 228                                   offset,
 229                                   BRW_SURFACEFORMAT_RAW,
 230                                   size,
 231                                   1,
 232                                   0 /* mocs */,
 233                                   true /* rw */);
 234 }
 235
 236 /**
 237  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 238  * read from this buffer with Data Port Read instructions/messages.
 239  */
 240 static void
 241 gen8_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 242 {
 243    struct gl_context *ctx = &brw->ctx;
 244
 245    /* _NEW_BUFFERS */
 246    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 247    uint32_t surf_index =
 248       brw->wm.prog_data->binding_table.render_target_start + unit;
 249
 250    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
 251                                     &brw->wm.base.surf_offset[surf_index]);
 252    memset(surf, 0, 13 * 4);
 253
 254    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 255              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 256              GEN8_SURFACE_TILING_Y;
 257    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 258              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 259 }
 260
 261 /**
 262  * Sets up a surface state structure to point at the given region.
 263  * While it is only used for the front/back buffer currently, it should be
 264  * usable for further buffers when doing ARB_draw_buffer support.
 265  */
 266 static void
 267 gen8_update_renderbuffer_surface(struct brw_context *brw,
 268                                  struct gl_renderbuffer *rb,
 269                                  bool layered,
 270                                  unsigned unit)
 271 {
 272    struct gl_context *ctx = &brw->ctx;
 273    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 274    struct intel_mipmap_tree *mt = irb->mt;
 275    uint32_t format = 0;
 276    uint32_t surf_type;
 277    bool is_array = false;
 278    int depth = MAX2(rb->Depth, 1);
 279    int min_array_element;
 280
 281    GLenum gl_target =
 282       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 283
 284    uint32_t surf_index =
 285       brw->wm.prog_data->binding_table.render_target_start + unit;
 286
 287    intel_miptree_used_for_rendering(mt);
 288
 289    /* Render targets can't use IMS layout. */
 290    assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 291
 292    switch (gl_target) {
 293    case GL_TEXTURE_CUBE_MAP_ARRAY:
 294    case GL_TEXTURE_CUBE_MAP:
 295       surf_type = BRW_SURFACE_2D;
 296       is_array = true;
 297       depth *= 6;
 298       break;
 299    default:
 300       surf_type = translate_tex_target(gl_target);
 301       is_array = _mesa_tex_target_is_array(gl_target);
 302       break;
 303    }
 304
 305    if (layered) {
 306       min_array_element = 0;
 307    } else if (mt->num_samples > 1) {
 308       min_array_element = irb->mt_layer / mt->num_samples;
 309    } else {
 310       min_array_element = irb->mt_layer;
 311    }
 312
 313    /* _NEW_BUFFERS */
 314    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 315    assert(brw_render_target_supported(brw, rb));
 316    format = brw->render_target_format[rb_format];
 317    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 318       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 319                     __FUNCTION__, _mesa_get_format_name(rb_format));
 320    }
 321
 322    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
 323                                     &brw->wm.base.surf_offset[surf_index]);
 324
 325    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 326              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 327              (format << BRW_SURFACE_FORMAT_SHIFT) |
 328              vertical_alignment(mt) |
 329              horizontal_alignment(mt) |
 330              surface_tiling_mode(mt->tiling);
 331
 332    surf[1] = SET_FIELD(BDW_MOCS_WT, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 333
 334    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 335              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 336
 337    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 338              (mt->pitch - 1); /* Surface Pitch */
 339
 340    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 341              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 342              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 343
 344    surf[5] = irb->mt_level - irb->mt->first_level;
 345
 346    surf[6] = 0; /* Nothing of relevance. */
 347
 348    surf[7] = mt->fast_clear_color_value |
 349              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 350              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 351              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 352              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 353
 354    *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
 355
 356    /* Nothing of relevance. */
 357    surf[10] = 0;
 358    surf[11] = 0;
 359    surf[12] = 0;
 360
 361    drm_intel_bo_emit_reloc(brw->batch.bo,
 362                            brw->wm.base.surf_offset[surf_index] + 8 * 4,
 363                            mt->bo,
 364                            0,
 365                            I915_GEM_DOMAIN_RENDER,
 366                            I915_GEM_DOMAIN_RENDER);
 367 }
 368
 369 void
 370 gen8_init_vtable_surface_functions(struct brw_context *brw)
 371 {
 372    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 373    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 374    brw->vtbl.update_null_renderbuffer_surface =
 375       gen8_update_null_renderbuffer_surface;
 376    brw->vtbl.create_raw_surface = gen8_create_raw_surface;
 377    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 378 }