src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "main/teximage.h"
  29 #include "program/prog_parameter.h"
  30 #include "program/prog_instruction.h"
  31
  32 #include "intel_mipmap_tree.h"
  33 #include "intel_batchbuffer.h"
  34 #include "intel_tex.h"
  35 #include "intel_fbo.h"
  36 #include "intel_buffer_objects.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41 #include "brw_wm.h"
  42
  43 /**
  44  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  45  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
  46  *
  47  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
  48  *         0          1          2          3             4            5
  49  *         4          5          6          7             0            1
  50  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
  51  *
  52  * which is simply adding 4 then modding by 8 (or anding with 7).
  53  */
  54 static unsigned
  55 swizzle_to_scs(unsigned swizzle)
  56 {
  57    return (swizzle + 4) & 7;
  58 }
  59
  60 static uint32_t
  61 surface_tiling_resource_mode(uint32_t tr_mode)
  62 {
  63    switch (tr_mode) {
  64    case INTEL_MIPTREE_TRMODE_YF:
  65       return GEN9_SURFACE_TRMODE_TILEYF;
  66    case INTEL_MIPTREE_TRMODE_YS:
  67       return GEN9_SURFACE_TRMODE_TILEYS;
  68    default:
  69       return GEN9_SURFACE_TRMODE_NONE;
  70    }
  71 }
  72
  73 static uint32_t
  74 surface_tiling_mode(uint32_t tiling)
  75 {
  76    switch (tiling) {
  77    case I915_TILING_X:
  78       return GEN8_SURFACE_TILING_X;
  79    case I915_TILING_Y:
  80       return GEN8_SURFACE_TILING_Y;
  81    default:
  82       return GEN8_SURFACE_TILING_NONE;
  83    }
  84 }
  85
  86 static unsigned
  87 vertical_alignment(const struct brw_context *brw,
  88                    const struct intel_mipmap_tree *mt,
  89                    uint32_t surf_type)
  90 {
  91    /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
  92     * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
  93     */
  94    if (brw->gen > 8 &&
  95        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
  96         surf_type == BRW_SURFACE_1D))
  97       return GEN8_SURFACE_VALIGN_4;
  98
  99    switch (mt->valign) {
 100    case 4:
 101       return GEN8_SURFACE_VALIGN_4;
 102    case 8:
 103       return GEN8_SURFACE_VALIGN_8;
 104    case 16:
 105       return GEN8_SURFACE_VALIGN_16;
 106    default:
 107       unreachable("Unsupported vertical surface alignment.");
 108    }
 109 }
 110
 111 static unsigned
 112 horizontal_alignment(const struct brw_context *brw,
 113                      const struct intel_mipmap_tree *mt,
 114                      uint32_t surf_type)
 115 {
 116    /* On Gen9+ horizontal alignment is ignored when tr_mode is not
 117     * TRMODE_NONE. Set to an arbitrary non-reserved value.
 118     */
 119    if (brw->gen > 8 &&
 120        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 121         gen9_use_linear_1d_layout(brw, mt)))
 122       return GEN8_SURFACE_HALIGN_4;
 123
 124    switch (mt->halign) {
 125    case 4:
 126       return GEN8_SURFACE_HALIGN_4;
 127    case 8:
 128       return GEN8_SURFACE_HALIGN_8;
 129    case 16:
 130       return GEN8_SURFACE_HALIGN_16;
 131    default:
 132       unreachable("Unsupported horizontal surface alignment.");
 133    }
 134 }
 135
 136 static uint32_t *
 137 allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
 138 {
 139    int dwords = brw->gen >= 9 ? 16 : 13;
 140    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 141                                       dwords * 4, 64, index, out_offset);
 142    memset(surf, 0, dwords * 4);
 143    return surf;
 144 }
 145
 146 static void
 147 gen8_emit_buffer_surface_state(struct brw_context *brw,
 148                                uint32_t *out_offset,
 149                                drm_intel_bo *bo,
 150                                unsigned buffer_offset,
 151                                unsigned surface_format,
 152                                unsigned buffer_size,
 153                                unsigned pitch,
 154                                bool rw)
 155 {
 156    const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 157    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 158
 159    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 160              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 161              BRW_SURFACE_RC_READ_WRITE;
 162    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
 163
 164    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 165              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 166    if (surface_format == BRW_SURFACEFORMAT_RAW)
 167       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
 168    else
 169       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 170    surf[3] |= (pitch - 1);
 171    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 172              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 173              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 174              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 175    /* reloc */
 176    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 177
 178    /* Emit relocation to surface contents. */
 179    if (bo) {
 180       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 181                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 182                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 183    }
 184 }
 185
 186 static void
 187 gen8_emit_fast_clear_color(struct brw_context *brw,
 188                            struct intel_mipmap_tree *mt,
 189                            uint32_t *surf)
 190 {
 191    if (brw->gen >= 9) {
 192       surf[12] = mt->gen9_fast_clear_color.ui[0];
 193       surf[13] = mt->gen9_fast_clear_color.ui[1];
 194       surf[14] = mt->gen9_fast_clear_color.ui[2];
 195       surf[15] = mt->gen9_fast_clear_color.ui[3];
 196    } else
 197       surf[7] |= mt->fast_clear_color_value;
 198 }
 199
 200 static void
 201 gen8_emit_texture_surface_state(struct brw_context *brw,
 202                                 struct intel_mipmap_tree *mt,
 203                                 GLenum target,
 204                                 unsigned min_layer, unsigned max_layer,
 205                                 unsigned min_level, unsigned max_level,
 206                                 unsigned format,
 207                                 unsigned swizzle,
 208                                 uint32_t *surf_offset,
 209                                 bool rw, bool for_gather)
 210 {
 211    const unsigned depth = max_layer - min_layer;
 212    struct intel_mipmap_tree *aux_mt = NULL;
 213    uint32_t aux_mode = 0;
 214    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 215    int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
 216    unsigned tiling_mode, pitch;
 217    const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 218    const uint32_t surf_type = translate_tex_target(target);
 219
 220    if (mt->format == MESA_FORMAT_S_UINT8) {
 221       tiling_mode = GEN8_SURFACE_TILING_W;
 222       pitch = 2 * mt->pitch;
 223    } else {
 224       tiling_mode = surface_tiling_mode(mt->tiling);
 225       pitch = mt->pitch;
 226    }
 227
 228    /* The MCS is not uploaded for single-sampled surfaces because the color
 229     * buffer should always have been resolved before it is used as a texture
 230     * so there is no need for it.
 231     */
 232    if (mt->mcs_mt && mt->num_samples > 1) {
 233       aux_mt = mt->mcs_mt;
 234       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 235
 236       /*
 237        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 238        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 239        *
 240        * From the hardware spec for GEN9:
 241        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 242        *  16 must be used."
 243        */
 244       if (brw->gen >= 9 || mt->num_samples == 1)
 245          assert(mt->halign == 16);
 246
 247       if (brw->gen >= 9) {
 248          assert(mt->num_samples > 1 ||
 249                 brw_losslessly_compressible_format(brw, surf_type));
 250       }
 251
 252    }
 253
 254    uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
 255
 256    surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
 257              format << BRW_SURFACE_FORMAT_SHIFT |
 258              vertical_alignment(brw, mt, surf_type) |
 259              horizontal_alignment(brw, mt, surf_type) |
 260              tiling_mode;
 261
 262    if (surf_type == BRW_SURFACE_CUBE) {
 263       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 264    }
 265
 266    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 267     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 268     *
 269     *    This bit must be set for the following surface types: BC2_UNORM
 270     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 271     */
 272    if ((brw->gen >= 9 || brw->is_cherryview) &&
 273        (format == BRW_SURFACEFORMAT_BC2_UNORM ||
 274         format == BRW_SURFACEFORMAT_BC3_UNORM ||
 275         format == BRW_SURFACEFORMAT_BC5_UNORM ||
 276         format == BRW_SURFACEFORMAT_BC5_SNORM ||
 277         format == BRW_SURFACEFORMAT_BC7_UNORM))
 278       surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
 279
 280    if (_mesa_is_array_texture(mt->target) || mt->target == GL_TEXTURE_CUBE_MAP)
 281       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 282
 283    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 284
 285    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 286              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 287
 288    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 289
 290    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 291              SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 292              SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 293
 294    surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 295              (max_level - min_level - 1); /* mip count */
 296
 297    if (brw->gen >= 9) {
 298       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 299       /* Disable Mip Tail by setting a large value. */
 300       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 301    }
 302
 303    if (aux_mt) {
 304       uint32_t tile_w, tile_h;
 305       assert(aux_mt->tiling == I915_TILING_Y);
 306       intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
 307                           aux_mt->cpp, &tile_w, &tile_h);
 308       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 309                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
 310                           GEN8_SURFACE_AUX_PITCH) |
 311                 aux_mode;
 312    }
 313
 314    gen8_emit_fast_clear_color(brw, mt, surf);
 315    surf[7] |=
 316       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 317       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 318       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 319       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 320
 321    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 322
 323    if (aux_mt) {
 324       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 325       drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
 326                               aux_mt->bo, 0,
 327                               I915_GEM_DOMAIN_SAMPLER,
 328                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 329    }
 330
 331    /* Emit relocation to surface contents */
 332    drm_intel_bo_emit_reloc(brw->batch.bo,
 333                            *surf_offset + 8 * 4,
 334                            mt->bo,
 335                            mt->offset,
 336                            I915_GEM_DOMAIN_SAMPLER,
 337                            (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 338 }
 339
 340 static void
 341 gen8_update_texture_surface(struct gl_context *ctx,
 342                             unsigned unit,
 343                             uint32_t *surf_offset,
 344                             bool for_gather)
 345 {
 346    struct brw_context *brw = brw_context(ctx);
 347    struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
 348
 349    if (obj->Target == GL_TEXTURE_BUFFER) {
 350       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 351
 352    } else {
 353       struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
 354       struct intel_texture_object *intel_obj = intel_texture_object(obj);
 355       struct intel_mipmap_tree *mt = intel_obj->mt;
 356       struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 357       /* If this is a view with restricted NumLayers, then our effective depth
 358        * is not just the miptree depth.
 359        */
 360       const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
 361                               obj->NumLayers : mt->logical_depth0);
 362
 363       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 364        * texturing functions that return a float, as our code generation always
 365        * selects the .x channel (which would always be 0).
 366        */
 367       const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
 368          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 369           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 370       const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
 371                                 brw_get_texture_swizzle(&brw->ctx, obj));
 372
 373       unsigned format = translate_tex_format(brw, intel_obj->_Format,
 374                                              sampler->sRGBDecode);
 375       if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
 376          mt = mt->stencil_mt;
 377          format = BRW_SURFACEFORMAT_R8_UINT;
 378       }
 379
 380       gen8_emit_texture_surface_state(brw, mt, obj->Target,
 381                                       obj->MinLayer, obj->MinLayer + depth,
 382                                       obj->MinLevel + obj->BaseLevel,
 383                                       obj->MinLevel + intel_obj->_MaxLevel + 1,
 384                                       format, swizzle, surf_offset,
 385                                       false, for_gather);
 386    }
 387 }
 388
 389 /**
 390  * Creates a null surface.
 391  *
 392  * This is used when the shader doesn't write to any color output.  An FB
 393  * write to target 0 will still be emitted, because that's how the thread is
 394  * terminated (and computed depth is returned), so we need to have the
 395  * hardware discard the target 0 color output..
 396  */
 397 static void
 398 gen8_emit_null_surface_state(struct brw_context *brw,
 399                              unsigned width,
 400                              unsigned height,
 401                              unsigned samples,
 402                              uint32_t *out_offset)
 403 {
 404    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 405
 406    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 407              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 408              GEN8_SURFACE_TILING_Y;
 409    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 410              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 411 }
 412
 413 /**
 414  * Sets up a surface state structure to point at the given region.
 415  * While it is only used for the front/back buffer currently, it should be
 416  * usable for further buffers when doing ARB_draw_buffer support.
 417  */
 418 static uint32_t
 419 gen8_update_renderbuffer_surface(struct brw_context *brw,
 420                                  struct gl_renderbuffer *rb,
 421                                  bool layered, unsigned unit /* unused */,
 422                                  uint32_t surf_index)
 423 {
 424    struct gl_context *ctx = &brw->ctx;
 425    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 426    struct intel_mipmap_tree *mt = irb->mt;
 427    struct intel_mipmap_tree *aux_mt = NULL;
 428    uint32_t aux_mode = 0;
 429    unsigned width = mt->logical_width0;
 430    unsigned height = mt->logical_height0;
 431    unsigned pitch = mt->pitch;
 432    uint32_t tiling = mt->tiling;
 433    unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 434    uint32_t format = 0;
 435    uint32_t surf_type;
 436    uint32_t offset;
 437    bool is_array = false;
 438    int depth = MAX2(irb->layer_count, 1);
 439    const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
 440       irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
 441    GLenum gl_target =
 442       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 443    const uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE;
 444
 445    intel_miptree_used_for_rendering(mt);
 446
 447    switch (gl_target) {
 448    case GL_TEXTURE_CUBE_MAP_ARRAY:
 449    case GL_TEXTURE_CUBE_MAP:
 450       surf_type = BRW_SURFACE_2D;
 451       is_array = true;
 452       depth *= 6;
 453       break;
 454    case GL_TEXTURE_3D:
 455       depth = MAX2(irb->mt->logical_depth0, 1);
 456       /* fallthrough */
 457    default:
 458       surf_type = translate_tex_target(gl_target);
 459       is_array = _mesa_is_array_texture(mt->target);
 460       break;
 461    }
 462
 463    /* _NEW_BUFFERS */
 464    /* Render targets can't use IMS layout. Stencil in turn gets configured as
 465     * single sampled and indexed manually by the program.
 466     */
 467    if (mt->format == MESA_FORMAT_S_UINT8) {
 468       brw_configure_w_tiled(mt, true, &width, &height, &pitch,
 469                             &tiling, &format);
 470    } else {
 471       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 472       assert(brw_render_target_supported(brw, rb));
 473       mesa_format rb_format = _mesa_get_render_format(ctx,
 474                                                       intel_rb_format(irb));
 475       format = brw->render_target_format[rb_format];
 476       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
 477          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 478                        __func__, _mesa_get_format_name(rb_format));
 479    }
 480
 481    if (mt->mcs_mt) {
 482       aux_mt = mt->mcs_mt;
 483       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 484
 485       /*
 486        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 487        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 488        *
 489        * From the hardware spec for GEN9:
 490        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 491        *  16 must be used."
 492        */
 493       if (brw->gen >= 9 || mt->num_samples == 1)
 494          assert(mt->halign == 16);
 495    }
 496
 497    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
 498
 499    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 500              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 501              (format << BRW_SURFACE_FORMAT_SHIFT) |
 502              vertical_alignment(brw, mt, surf_type) |
 503              horizontal_alignment(brw, mt, surf_type) |
 504              surface_tiling_mode(tiling);
 505
 506    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 507
 508    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 509              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 510
 511    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 512              (pitch - 1); /* Surface Pitch */
 513
 514    surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 515              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 516
 517    if (mt->format != MESA_FORMAT_S_UINT8)
 518       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 519
 520    surf[5] = irb->mt_level - irb->mt->first_level;
 521
 522    if (brw->gen >= 9) {
 523       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 524       /* Disable Mip Tail by setting a large value. */
 525       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 526    }
 527
 528    if (aux_mt) {
 529       uint32_t tile_w, tile_h;
 530       assert(aux_mt->tiling == I915_TILING_Y);
 531       intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
 532                           aux_mt->cpp, &tile_w, &tile_h);
 533       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 534                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
 535                           GEN8_SURFACE_AUX_PITCH) |
 536                 aux_mode;
 537    }
 538
 539    gen8_emit_fast_clear_color(brw, mt, surf);
 540    surf[7] |= SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 541               SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 542               SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 543               SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 544
 545    assert(mt->offset % mt->cpp == 0);
 546    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 547
 548    if (aux_mt) {
 549       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 550       drm_intel_bo_emit_reloc(brw->batch.bo,
 551                               offset + 10 * 4,
 552                               aux_mt->bo, 0,
 553                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 554    }
 555
 556    drm_intel_bo_emit_reloc(brw->batch.bo,
 557                            offset + 8 * 4,
 558                            mt->bo,
 559                            mt->offset,
 560                            I915_GEM_DOMAIN_RENDER,
 561                            I915_GEM_DOMAIN_RENDER);
 562
 563    return offset;
 564 }
 565
 566 void
 567 gen8_init_vtable_surface_functions(struct brw_context *brw)
 568 {
 569    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 570    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 571    brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
 572    brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
 573    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 574 }