src/mesa/drivers/dri/i965/gen8_surface_state.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/blend.h"
  25 #include "main/mtypes.h"
  26 #include "main/samplerobj.h"
  27 #include "main/texformat.h"
  28 #include "main/teximage.h"
  29 #include "program/prog_parameter.h"
  30 #include "program/prog_instruction.h"
  31
  32 #include "intel_mipmap_tree.h"
  33 #include "intel_batchbuffer.h"
  34 #include "intel_tex.h"
  35 #include "intel_fbo.h"
  36 #include "intel_buffer_objects.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41 #include "brw_wm.h"
  42
  43 /**
  44  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  45  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
  46  *
  47  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
  48  *         0          1          2          3             4            5
  49  *         4          5          6          7             0            1
  50  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
  51  *
  52  * which is simply adding 4 then modding by 8 (or anding with 7).
  53  */
  54 static unsigned
  55 swizzle_to_scs(unsigned swizzle)
  56 {
  57    return (swizzle + 4) & 7;
  58 }
  59
  60 static uint32_t
  61 surface_tiling_resource_mode(uint32_t tr_mode)
  62 {
  63    switch (tr_mode) {
  64    case INTEL_MIPTREE_TRMODE_YF:
  65       return GEN9_SURFACE_TRMODE_TILEYF;
  66    case INTEL_MIPTREE_TRMODE_YS:
  67       return GEN9_SURFACE_TRMODE_TILEYS;
  68    default:
  69       return GEN9_SURFACE_TRMODE_NONE;
  70    }
  71 }
  72
  73 static uint32_t
  74 surface_tiling_mode(uint32_t tiling)
  75 {
  76    switch (tiling) {
  77    case I915_TILING_X:
  78       return GEN8_SURFACE_TILING_X;
  79    case I915_TILING_Y:
  80       return GEN8_SURFACE_TILING_Y;
  81    default:
  82       return GEN8_SURFACE_TILING_NONE;
  83    }
  84 }
  85
  86 static unsigned
  87 vertical_alignment(const struct brw_context *brw,
  88                    const struct intel_mipmap_tree *mt,
  89                    uint32_t surf_type)
  90 {
  91    /* On Gen9+ vertical alignment is ignored for 1D surfaces and when
  92     * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value.
  93     */
  94    if (brw->gen > 8 &&
  95        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
  96         surf_type == BRW_SURFACE_1D))
  97       return GEN8_SURFACE_VALIGN_4;
  98
  99    switch (mt->valign) {
 100    case 4:
 101       return GEN8_SURFACE_VALIGN_4;
 102    case 8:
 103       return GEN8_SURFACE_VALIGN_8;
 104    case 16:
 105       return GEN8_SURFACE_VALIGN_16;
 106    default:
 107       unreachable("Unsupported vertical surface alignment.");
 108    }
 109 }
 110
 111 static unsigned
 112 horizontal_alignment(const struct brw_context *brw,
 113                      const struct intel_mipmap_tree *mt,
 114                      uint32_t surf_type)
 115 {
 116    /* On Gen9+ horizontal alignment is ignored when tr_mode is not
 117     * TRMODE_NONE. Set to an arbitrary non-reserved value.
 118     */
 119    if (brw->gen > 8 &&
 120        (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 121         gen9_use_linear_1d_layout(brw, mt)))
 122       return GEN8_SURFACE_HALIGN_4;
 123
 124    switch (mt->halign) {
 125    case 4:
 126       return GEN8_SURFACE_HALIGN_4;
 127    case 8:
 128       return GEN8_SURFACE_HALIGN_8;
 129    case 16:
 130       return GEN8_SURFACE_HALIGN_16;
 131    default:
 132       unreachable("Unsupported horizontal surface alignment.");
 133    }
 134 }
 135
 136 static uint32_t *
 137 allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
 138 {
 139    int dwords = brw->gen >= 9 ? 16 : 13;
 140    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 141                                       dwords * 4, 64, index, out_offset);
 142    memset(surf, 0, dwords * 4);
 143    return surf;
 144 }
 145
 146 static void
 147 gen8_emit_buffer_surface_state(struct brw_context *brw,
 148                                uint32_t *out_offset,
 149                                drm_intel_bo *bo,
 150                                unsigned buffer_offset,
 151                                unsigned surface_format,
 152                                unsigned buffer_size,
 153                                unsigned pitch,
 154                                bool rw)
 155 {
 156    const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 157    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 158
 159    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 160              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 161              BRW_SURFACE_RC_READ_WRITE;
 162    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
 163
 164    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 165              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 166    if (surface_format == BRW_SURFACEFORMAT_RAW)
 167       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
 168    else
 169       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 170    surf[3] |= (pitch - 1);
 171    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 172              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 173              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 174              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 175    /* reloc */
 176    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
 177
 178    /* Emit relocation to surface contents. */
 179    if (bo) {
 180       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
 181                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 182                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
 183    }
 184 }
 185
 186 static void
 187 gen8_emit_fast_clear_color(struct brw_context *brw,
 188                            struct intel_mipmap_tree *mt,
 189                            uint32_t *surf)
 190 {
 191    if (brw->gen >= 9) {
 192       surf[12] = mt->gen9_fast_clear_color.ui[0];
 193       surf[13] = mt->gen9_fast_clear_color.ui[1];
 194       surf[14] = mt->gen9_fast_clear_color.ui[2];
 195       surf[15] = mt->gen9_fast_clear_color.ui[3];
 196    } else
 197       surf[7] |= mt->fast_clear_color_value;
 198 }
 199
 200 static void
 201 gen8_emit_texture_surface_state(struct brw_context *brw,
 202                                 struct intel_mipmap_tree *mt,
 203                                 GLenum target,
 204                                 unsigned min_layer, unsigned max_layer,
 205                                 unsigned min_level, unsigned max_level,
 206                                 unsigned format,
 207                                 unsigned swizzle,
 208                                 uint32_t *surf_offset,
 209                                 bool rw, bool for_gather)
 210 {
 211    const unsigned depth = max_layer - min_layer;
 212    struct intel_mipmap_tree *aux_mt = NULL;
 213    uint32_t aux_mode = 0;
 214    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 215    int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
 216    unsigned tiling_mode, pitch;
 217    const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 218    const uint32_t surf_type = translate_tex_target(target);
 219
 220    if (mt->format == MESA_FORMAT_S_UINT8) {
 221       tiling_mode = GEN8_SURFACE_TILING_W;
 222       pitch = 2 * mt->pitch;
 223    } else {
 224       tiling_mode = surface_tiling_mode(mt->tiling);
 225       pitch = mt->pitch;
 226    }
 227
 228    if (mt->mcs_mt) {
 229       aux_mt = mt->mcs_mt;
 230       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 231
 232       /*
 233        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 234        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 235        *
 236        * From the hardware spec for GEN9:
 237        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 238        *  16 must be used."
 239        */
 240       if (brw->gen >= 9 || mt->num_samples == 1)
 241          assert(mt->halign == 16);
 242
 243       if (brw->gen >= 9) {
 244          assert(mt->num_samples > 1 ||
 245                 brw_losslessly_compressible_format(brw, surf_type));
 246       }
 247
 248    }
 249
 250    uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
 251
 252    surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
 253              format << BRW_SURFACE_FORMAT_SHIFT |
 254              vertical_alignment(brw, mt, surf_type) |
 255              horizontal_alignment(brw, mt, surf_type) |
 256              tiling_mode;
 257
 258    if (surf_type == BRW_SURFACE_CUBE) {
 259       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 260    }
 261
 262    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 263     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 264     *
 265     *    This bit must be set for the following surface types: BC2_UNORM
 266     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 267     */
 268    if ((brw->gen >= 9 || brw->is_cherryview) &&
 269        (format == BRW_SURFACEFORMAT_BC2_UNORM ||
 270         format == BRW_SURFACEFORMAT_BC3_UNORM ||
 271         format == BRW_SURFACEFORMAT_BC5_UNORM ||
 272         format == BRW_SURFACEFORMAT_BC5_SNORM ||
 273         format == BRW_SURFACEFORMAT_BC7_UNORM))
 274       surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
 275
 276    if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
 277       surf[0] |= GEN8_SURFACE_IS_ARRAY;
 278
 279    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 280
 281    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 282              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 283
 284    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 285
 286    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 287              SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 288              SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 289
 290    surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 291              (max_level - min_level - 1); /* mip count */
 292
 293    if (brw->gen >= 9) {
 294       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 295       /* Disable Mip Tail by setting a large value. */
 296       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 297    }
 298
 299    if (aux_mt) {
 300       uint32_t tile_w, tile_h;
 301       assert(aux_mt->tiling == I915_TILING_Y);
 302       intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
 303                           aux_mt->cpp, &tile_w, &tile_h);
 304       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 305                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
 306                           GEN8_SURFACE_AUX_PITCH) |
 307                 aux_mode;
 308    }
 309
 310    gen8_emit_fast_clear_color(brw, mt, surf);
 311    surf[7] |=
 312       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 313       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 314       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 315       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 316
 317    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 318
 319    if (aux_mt) {
 320       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 321       drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
 322                               aux_mt->bo, 0,
 323                               I915_GEM_DOMAIN_SAMPLER,
 324                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 325    }
 326
 327    /* Emit relocation to surface contents */
 328    drm_intel_bo_emit_reloc(brw->batch.bo,
 329                            *surf_offset + 8 * 4,
 330                            mt->bo,
 331                            mt->offset,
 332                            I915_GEM_DOMAIN_SAMPLER,
 333                            (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 334 }
 335
 336 static void
 337 gen8_update_texture_surface(struct gl_context *ctx,
 338                             unsigned unit,
 339                             uint32_t *surf_offset,
 340                             bool for_gather)
 341 {
 342    struct brw_context *brw = brw_context(ctx);
 343    struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
 344
 345    if (obj->Target == GL_TEXTURE_BUFFER) {
 346       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 347
 348    } else {
 349       struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
 350       struct intel_texture_object *intel_obj = intel_texture_object(obj);
 351       struct intel_mipmap_tree *mt = intel_obj->mt;
 352       struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 353       /* If this is a view with restricted NumLayers, then our effective depth
 354        * is not just the miptree depth.
 355        */
 356       const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
 357                               obj->NumLayers : mt->logical_depth0);
 358
 359       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 360        * texturing functions that return a float, as our code generation always
 361        * selects the .x channel (which would always be 0).
 362        */
 363       const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
 364          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 365           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 366       const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
 367                                 brw_get_texture_swizzle(&brw->ctx, obj));
 368
 369       unsigned format = translate_tex_format(brw, intel_obj->_Format,
 370                                              sampler->sRGBDecode);
 371       if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
 372          mt = mt->stencil_mt;
 373          format = BRW_SURFACEFORMAT_R8_UINT;
 374       }
 375
 376       gen8_emit_texture_surface_state(brw, mt, obj->Target,
 377                                       obj->MinLayer, obj->MinLayer + depth,
 378                                       obj->MinLevel + obj->BaseLevel,
 379                                       obj->MinLevel + intel_obj->_MaxLevel + 1,
 380                                       format, swizzle, surf_offset,
 381                                       false, for_gather);
 382    }
 383 }
 384
 385 /**
 386  * Creates a null surface.
 387  *
 388  * This is used when the shader doesn't write to any color output.  An FB
 389  * write to target 0 will still be emitted, because that's how the thread is
 390  * terminated (and computed depth is returned), so we need to have the
 391  * hardware discard the target 0 color output..
 392  */
 393 static void
 394 gen8_emit_null_surface_state(struct brw_context *brw,
 395                              unsigned width,
 396                              unsigned height,
 397                              unsigned samples,
 398                              uint32_t *out_offset)
 399 {
 400    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
 401
 402    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 403              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 404              GEN8_SURFACE_TILING_Y;
 405    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 406              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 407 }
 408
 409 /**
 410  * Sets up a surface state structure to point at the given region.
 411  * While it is only used for the front/back buffer currently, it should be
 412  * usable for further buffers when doing ARB_draw_buffer support.
 413  */
 414 static uint32_t
 415 gen8_update_renderbuffer_surface(struct brw_context *brw,
 416                                  struct gl_renderbuffer *rb,
 417                                  bool layered, unsigned unit /* unused */,
 418                                  uint32_t surf_index)
 419 {
 420    struct gl_context *ctx = &brw->ctx;
 421    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 422    struct intel_mipmap_tree *mt = irb->mt;
 423    struct intel_mipmap_tree *aux_mt = NULL;
 424    uint32_t aux_mode = 0;
 425    unsigned width = mt->logical_width0;
 426    unsigned height = mt->logical_height0;
 427    unsigned pitch = mt->pitch;
 428    uint32_t tiling = mt->tiling;
 429    unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
 430    uint32_t format = 0;
 431    uint32_t surf_type;
 432    uint32_t offset;
 433    bool is_array = false;
 434    int depth = MAX2(irb->layer_count, 1);
 435    const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
 436       irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
 437    GLenum gl_target =
 438       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 439    const uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE;
 440
 441    intel_miptree_used_for_rendering(mt);
 442
 443    switch (gl_target) {
 444    case GL_TEXTURE_CUBE_MAP_ARRAY:
 445    case GL_TEXTURE_CUBE_MAP:
 446       surf_type = BRW_SURFACE_2D;
 447       is_array = true;
 448       depth *= 6;
 449       break;
 450    case GL_TEXTURE_3D:
 451       depth = MAX2(irb->mt->logical_depth0, 1);
 452       /* fallthrough */
 453    default:
 454       surf_type = translate_tex_target(gl_target);
 455       is_array = _mesa_tex_target_is_array(gl_target);
 456       break;
 457    }
 458
 459    /* _NEW_BUFFERS */
 460    /* Render targets can't use IMS layout. Stencil in turn gets configured as
 461     * single sampled and indexed manually by the program.
 462     */
 463    if (mt->format == MESA_FORMAT_S_UINT8) {
 464       brw_configure_w_tiled(mt, true, &width, &height, &pitch,
 465                             &tiling, &format);
 466    } else {
 467       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 468       assert(brw_render_target_supported(brw, rb));
 469       mesa_format rb_format = _mesa_get_render_format(ctx,
 470                                                       intel_rb_format(irb));
 471       format = brw->render_target_format[rb_format];
 472       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
 473          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 474                        __func__, _mesa_get_format_name(rb_format));
 475    }
 476
 477    if (mt->mcs_mt) {
 478       aux_mt = mt->mcs_mt;
 479       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
 480
 481       /*
 482        * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
 483        * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
 484        *
 485        * From the hardware spec for GEN9:
 486        * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
 487        *  16 must be used."
 488        */
 489       if (brw->gen >= 9 || mt->num_samples == 1)
 490          assert(mt->halign == 16);
 491    }
 492
 493    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
 494
 495    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
 496              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
 497              (format << BRW_SURFACE_FORMAT_SHIFT) |
 498              vertical_alignment(brw, mt, surf_type) |
 499              horizontal_alignment(brw, mt, surf_type) |
 500              surface_tiling_mode(tiling);
 501
 502    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
 503
 504    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 505              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 506
 507    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 508              (pitch - 1); /* Surface Pitch */
 509
 510    surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 511              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 512
 513    if (mt->format != MESA_FORMAT_S_UINT8)
 514       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 515
 516    surf[5] = irb->mt_level - irb->mt->first_level;
 517
 518    if (brw->gen >= 9) {
 519       surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
 520       /* Disable Mip Tail by setting a large value. */
 521       surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
 522    }
 523
 524    if (aux_mt) {
 525       uint32_t tile_w, tile_h;
 526       assert(aux_mt->tiling == I915_TILING_Y);
 527       intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
 528                           aux_mt->cpp, &tile_w, &tile_h);
 529       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
 530                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
 531                           GEN8_SURFACE_AUX_PITCH) |
 532                 aux_mode;
 533    }
 534
 535    gen8_emit_fast_clear_color(brw, mt, surf);
 536    surf[7] |= SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 537               SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 538               SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 539               SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 540
 541    assert(mt->offset % mt->cpp == 0);
 542    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 543
 544    if (aux_mt) {
 545       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
 546       drm_intel_bo_emit_reloc(brw->batch.bo,
 547                               offset + 10 * 4,
 548                               aux_mt->bo, 0,
 549                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 550    }
 551
 552    drm_intel_bo_emit_reloc(brw->batch.bo,
 553                            offset + 8 * 4,
 554                            mt->bo,
 555                            mt->offset,
 556                            I915_GEM_DOMAIN_RENDER,
 557                            I915_GEM_DOMAIN_RENDER);
 558
 559    return offset;
 560 }
 561
 562 void
 563 gen8_init_vtable_surface_functions(struct brw_context *brw)
 564 {
 565    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
 566    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
 567    brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
 568    brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
 569    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
 570 }