src/mesa/drivers/dri/i965/gen8_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32 static void
  33 upload_vs_state(struct brw_context *brw)
  34 {
  35    struct gl_context *ctx = &brw->ctx;
  36    const struct brw_stage_state *stage_state = &brw->vs.base;
  37    uint32_t floating_point_mode = 0;
  38
  39    /* BRW_NEW_VS_PROG_DATA */
  40    const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base;
  41
  42    assert(prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
  43           prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
  44
  45    if (prog_data->base.use_alt_mode)
  46       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
  47
  48    BEGIN_BATCH(9);
  49    OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
  50    OUT_BATCH(stage_state->prog_offset);
  51    OUT_BATCH(0);
  52    OUT_BATCH(floating_point_mode |
  53              ((ALIGN(stage_state->sampler_count, 4) / 4) <<
  54                GEN6_VS_SAMPLER_COUNT_SHIFT) |
  55              ((prog_data->base.binding_table.size_bytes / 4) <<
  56                GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  57
  58    if (prog_data->base.total_scratch) {
  59       OUT_RELOC64(stage_state->scratch_bo,
  60                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  61                   ffs(prog_data->base.total_scratch) - 11);
  62    } else {
  63       OUT_BATCH(0);
  64       OUT_BATCH(0);
  65    }
  66
  67    OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
  68               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
  69              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
  70              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
  71
  72    uint32_t simd8_enable = prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ?
  73       GEN8_VS_SIMD8_ENABLE : 0;
  74    OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
  75              GEN6_VS_STATISTICS_ENABLE |
  76              simd8_enable |
  77              GEN6_VS_ENABLE);
  78
  79    /* _NEW_TRANSFORM */
  80    OUT_BATCH((ctx->Transform.ClipPlanesEnabled <<
  81               GEN8_VS_USER_CLIP_DISTANCE_SHIFT));
  82    ADVANCE_BATCH();
  83 }
  84
  85 const struct brw_tracked_state gen8_vs_state = {
  86    .dirty = {
  87       .mesa  = _NEW_TRANSFORM,
  88       .brw   = BRW_NEW_BATCH |
  89                BRW_NEW_CONTEXT |
  90                BRW_NEW_VS_PROG_DATA,
  91    },
  92    .emit = upload_vs_state,
  93 };